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authorMatt DeVillier <matt.devillier@gmail.com>2018-02-19 17:35:55 -0600
committerMartin Roth <martinroth@google.com>2018-03-01 16:10:25 +0000
commit0f49bbceef3ee4d0755c5784c3dd647528b3c7bc (patch)
treed8a0a74920d20a3ba3fbe134496036458dd42259 /src
parent81a6f109bab8f58984603fbd534e2548be290480 (diff)
downloadcoreboot-0f49bbceef3ee4d0755c5784c3dd647528b3c7bc.tar.xz
soc/intel/broadwell: Generate ACPI DMAR table
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/broadwell/acpi.c57
-rw-r--r--src/soc/intel/broadwell/chip.c12
-rw-r--r--src/soc/intel/broadwell/include/soc/acpi.h3
3 files changed, 67 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index a23c8e2f4d..69c1eb81dc 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -37,6 +37,7 @@
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
+#include <soc/systemagent.h>
#include <soc/intel/broadwell/chip.h>
/*
@@ -571,6 +572,62 @@ void generate_cpu_entries(device_t device)
}
}
+static unsigned long acpi_fill_dmar(unsigned long current)
+{
+ struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+ const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
+ const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
+ const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
+ const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
+
+ /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
+ if (igfx_dev && igfx_dev->enabled && gfxvtbar
+ && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
+ const unsigned long tmp = current;
+
+ current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
+ current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);
+
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+
+ /* VTVC0BAR has to be set, enabled, and in 32-bit space */
+ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
+ const unsigned long tmp = current;
+ current += acpi_create_dmar_drhd(current,
+ DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+ current += acpi_create_dmar_drhd_ds_ioapic(current,
+ 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
+ size_t i;
+ for (i = 0; i < 8; ++i)
+ current += acpi_create_dmar_drhd_ds_msi_hpet(current,
+ 0, PCH_HPET_PCI_BUS,
+ PCH_HPET_PCI_SLOT, i);
+ acpi_dmar_drhd_fixup(tmp, current);
+ }
+
+ return current;
+}
+
+unsigned long northbridge_write_acpi_tables(struct device *const dev,
+ unsigned long current,
+ struct acpi_rsdp *const rsdp)
+{
+ /* Create DMAR table only if we have VT-d capability. */
+ const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
+ if (capid0_a & VTD_DISABLE)
+ return current;
+
+ acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
+ printk(BIOS_DEBUG, "ACPI: * DMAR\n");
+ acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
+ current += dmar->header.length;
+ current = acpi_align_current(current);
+ acpi_add_table(rsdp, dmar);
+
+ return current;
+}
+
unsigned long acpi_madt_irq_overrides(unsigned long current)
{
int sci = acpi_sci_irq();
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index 8176c8ecda..c282c6b14a 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/intel/broadwell/chip.h>
@@ -26,10 +27,13 @@ static void pci_domain_set_resources(device_t dev)
}
static struct device_operations pci_domain_ops = {
- .read_resources = &pci_domain_read_resources,
- .set_resources = &pci_domain_set_resources,
- .scan_bus = &pci_domain_scan_bus,
- .ops_pci_bus = &pci_bus_default_ops,
+ .read_resources = &pci_domain_read_resources,
+ .set_resources = &pci_domain_set_resources,
+ .scan_bus = &pci_domain_scan_bus,
+ .ops_pci_bus = &pci_bus_default_ops,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .write_acpi_tables = &northbridge_write_acpi_tables,
+#endif
};
static struct device_operations cpu_bus_ops = {
diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h
index f766dc953a..24fe3ae7aa 100644
--- a/src/soc/intel/broadwell/include/soc/acpi.h
+++ b/src/soc/intel/broadwell/include/soc/acpi.h
@@ -29,5 +29,6 @@ void acpi_create_intel_hpet(acpi_hpet_t *hpet);
void acpi_fill_in_fadt(acpi_fadt_t *fadt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_init_gnvs(global_nvs_t *gnvs);
-
+unsigned long northbridge_write_acpi_tables(struct device *dev,
+ unsigned long current, struct acpi_rsdp *rsdp);
#endif