Remove various .c #includes from Intel 440BX/82371EB boards.

 - Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c
   into distinct compilation units, and don't #include the files anymore
   in romstage.c files.

 - Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and
   northbridge/intel/i440bx/debug.c.

 - Add various header files which are now needed.

 - Make functions that need to be visible non-static.

 - Drop a remaining "select ROMCC" from a 4440BX board.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

31 files changed, 155 insertions, 140 deletions

diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c
index b32f10b102..cf44109e06 100644
--- a/src/mainboard/a-trend/atc-6220/romstage.c
+++ b/src/mainboard/a-trend/atc-6220/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c
index 4384c2387f..cddaffb41c 100644
--- a/src/mainboard/a-trend/atc-6240/romstage.c
+++ b/src/mainboard/a-trend/atc-6240/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c
index ca2a56e3cf..101b1f06fb 100644
--- a/src/mainboard/abit/be6-ii_v2_0/romstage.c
+++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -39,14 +38,14 @@
 /* FIXME: It's a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: It's a Winbond W83977EF, actually. */
diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c
index 2fc26aba16..c5822a566b 100644
--- a/src/mainboard/asus/p2b-d/romstage.c
+++ b/src/mainboard/asus/p2b-d/romstage.c
@@ -27,7 +27,7 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
@@ -38,14 +38,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	enable_lapic();		/* FIXME? */
diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c
index 002ff93ea9..a2341b21b7 100644
--- a/src/mainboard/asus/p2b-ds/romstage.c
+++ b/src/mainboard/asus/p2b-ds/romstage.c
@@ -27,9 +27,8 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -38,14 +37,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	enable_lapic();		/* FIXME? */
diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c
index 40277c459f..41926d0bd3 100644
--- a/src/mainboard/asus/p2b-f/romstage.c
+++ b/src/mainboard/asus/p2b-f/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -39,14 +38,14 @@
 /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c
index a1018fbaa8..b480aa55c2 100644
--- a/src/mainboard/asus/p2b-ls/romstage.c
+++ b/src/mainboard/asus/p2b-ls/romstage.c
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
@@ -38,14 +38,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c
index b32f10b102..cf44109e06 100644
--- a/src/mainboard/asus/p2b/romstage.c
+++ b/src/mainboard/asus/p2b/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index 8d8c0b39d8..04fa6a73c3 100644
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -26,10 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
-#include "southbridge/intel/i82371eb/i82371eb_early_pm.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,17 +35,18 @@
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 #include <lib.h>
 
+void enable_pm(void);
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 /*
  * ASUS P3B-F specific SPD enable magic.
  *
diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c
index 67d7b92ca9..9d97c87dfc 100644
--- a/src/mainboard/azza/pt-6ibd/romstage.c
+++ b/src/mainboard/azza/pt-6ibd/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -39,14 +38,14 @@
 /* FIXME: It's a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: It's a Winbond W83977EF, actually. */
diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c
index d00fc773ea..d341e4c8b5 100644
--- a/src/mainboard/biostar/m6tba/romstage.c
+++ b/src/mainboard/biostar/m6tba/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
index 66ef32fa66..0f317809b7 100644
--- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -39,14 +38,14 @@
 /* FIXME: This should be PC97307 (but it's buggy at the moment)! */
 #define SERIAL_DEV PNP_DEV(0x15c, PC97317_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: Should be PC97307! */
diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c
index 13e1ff71d3..17bf59d03a 100644
--- a/src/mainboard/gigabyte/ga-6bxc/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -38,14 +37,14 @@ void it8671f_48mhz_clkin(void);
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c
index e60ca46fa8..b93b87f0e7 100644
--- a/src/mainboard/gigabyte/ga-6bxe/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c
@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
@@ -38,14 +38,14 @@ static void it8671f_48mhz_clkin(void);
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	it8671f_48mhz_clkin();
diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c
index 5dde6c4e55..23b727733e 100644
--- a/src/mainboard/msi/ms6119/romstage.c
+++ b/src/mainboard/msi/ms6119/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c
index dfa9c993ae..2740abb7a8 100644
--- a/src/mainboard/msi/ms6147/romstage.c
+++ b/src/mainboard/msi/ms6147/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include <cpu/x86/bist.h>
@@ -37,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c
index 4e25f093b7..630f313b1b 100644
--- a/src/mainboard/msi/ms6156/romstage.c
+++ b/src/mainboard/msi/ms6156/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig
index be09194ad4..cf6bb1dd52 100644
--- a/src/mainboard/nokia/ip530/Kconfig
+++ b/src/mainboard/nokia/ip530/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOUTHBRIDGE_TI_PCI1X2X
 	select DRIVERS_DEC_21143
 	select BOARD_ROMSIZE_KB_256
-	select ROMCC
 	select PIRQ_ROUTE
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c
index f508fc6dc6..fdffbf9d06 100644
--- a/src/mainboard/nokia/ip530/romstage.c
+++ b/src/mainboard/nokia/ip530/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
index c608aac86a..99eb7b6b71 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -38,14 +37,14 @@ void it8671f_48mhz_clkin(void);
 
 #define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c
index 599dcdfc85..8cb436be0f 100644
--- a/src/mainboard/tyan/s1846/romstage.c
+++ b/src/mainboard/tyan/s1846/romstage.c
@@ -26,9 +26,8 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc
index 16d702a24e..0c0a3c846d 100644
--- a/src/northbridge/intel/i440bx/Makefile.inc
+++ b/src/northbridge/intel/i440bx/Makefile.inc
@@ -20,3 +20,6 @@
 
 driver-y += northbridge.c
 
+romstage-y += raminit.c
+romstage-y += debug.c
+
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index 6f253bd941..d5748737b6 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -1,4 +1,6 @@
-static void dump_spd_registers(void)
+#include "raminit.h"
+
+void dump_spd_registers(void)
 {
 #if CONFIG_DEBUG_RAM_SETUP
 	int i;
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index ebcd368511..9a5968d592 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -21,7 +21,12 @@
 
 #include <spd.h>
 #include <delay.h>
+#include <stdint.h>
 #include <stdlib.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
 #include "i440bx.h"
 #include "raminit.h"
 
@@ -630,7 +635,7 @@ static void spd_enable_refresh(void)
 Public interface.
 -----------------------------------------------------------------------------*/
 
-static void sdram_set_registers(void)
+void sdram_set_registers(void)
 {
 	int i, max;
 	uint8_t reg;
@@ -956,7 +961,7 @@ static void set_dram_row_attributes(void)
 	PRINT_DEBUG("\n");
 }
 
-static void sdram_set_spd_registers(void)
+void sdram_set_spd_registers(void)
 {
 	/* Setup DRAM row boundary registers and other attributes. */
 	set_dram_row_attributes();
@@ -972,7 +977,7 @@ static void sdram_set_spd_registers(void)
 	pci_write_config8(NB, DRAMT, 0x03);
 }
 
-static void sdram_enable(void)
+void sdram_enable(void)
 {
 	int i;
 
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index d05f6fd8c9..18268a1e82 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -26,5 +26,12 @@
 
 /* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */
 #define DIMM_SPD_BASE	0x50
+ 
+/* Function prototypes. */
+int spd_read_byte(unsigned int device, unsigned int address);
+void sdram_set_registers(void);
+void sdram_set_spd_registers(void);
+void sdram_enable(void);
+void dump_spd_registers(void);
 
 #endif				/* RAMINIT_H */
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index 24892f242d..816ef1bcc3 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -25,4 +25,6 @@ driver-y +=  i82371eb_usb.c
 driver-y +=  i82371eb_smbus.c
 driver-y +=  i82371eb_reset.c
 
-#romstage-y += i82371eb_early_rom.c
+romstage-y += i82371eb_early_pm.c
+romstage-y += i82371eb_early_smbus.c
+
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 1093766dbe..0536c54541 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -21,10 +21,17 @@
 #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 
+#if !defined(ASSEMBLY)
 #if !defined(__PRE_RAM__)
+
+#include <arch/io.h>
+#include <device/device.h>
 #include "chip.h"
+
 void i82371eb_enable(device_t dev);
 void i82371eb_hard_reset(void);
+
+#endif
 #endif
 
 /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
@@ -55,6 +62,8 @@ void i82371eb_hard_reset(void);
 #define PMBA		0x40	/* Power management base address */
 #define PMREGMISC	0x80	/* Miscellaneous power management */
 
+#define PM_IO_BASE	0xe400
+
 /* Bit definitions */
 #define EXT_BIOS_ENABLE_1MB	(1 << 9)  /* 1-Meg Extended BIOS Enable */
 #define EXT_BIOS_ENABLE		(1 << 7)  /* Extended BIOS Enable */
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
index e6dd68eb7a..ad5fe7cfd8 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
@@ -19,24 +19,25 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
+#include <console/console.h>
 #include "i82371eb.h"
 
-#define PM_IO_BASE 0xe400
+void enable_pm(void);
 
-static void enable_pm(void)
+void enable_pm(void)
 {
 	device_t dev;
 	u8 reg8;
 	u16 reg16;
 
-	/* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */
+	/* Get the SMBus/PM device of the 82371AB/EB/MB. */
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
 				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
 
-	if (dev == PCI_DEV_INVALID)
-		die("SMBus/PM controller not found\n");
-
 	/* Set the PM I/O base. */
 	pci_write_config32(dev, PMBA, PM_IO_BASE | 1);
 
@@ -50,4 +51,3 @@ static void enable_pm(void)
 	reg8 |= PMIOSE;
 	pci_write_config8(dev, PMREGMISC, reg8);
 }
-
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
index 76ae9f50b2..0ae5667e86 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
@@ -18,28 +18,29 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* TODO: Implement smbus_write_byte(), smbus_recv_byte(), smbus_send_byte(). */
-
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
 #include <device/pci_ids.h>
+#include <device/pci_def.h>
 #include "i82371eb.h"
 #include "i82371eb_smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 
-static void enable_smbus(void)
+int smbus_read_byte(u8 device, u8 address);
+
+void enable_smbus(void)
 {
 	device_t dev;
 	u8 reg8;
 	u16 reg16;
 
-	/* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */
+	/* Get the SMBus/PM device of the 82371AB/EB/MB. */
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
 				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
 
-	if (dev == PCI_DEV_INVALID)
-		die("SMBus/PM controller not found\n");
-
 	/* Set the SMBus I/O base. */
 	pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
 
@@ -57,7 +58,7 @@ static void enable_smbus(void)
 	outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
 }
 
-static int smbus_read_byte(u8 device, u8 address)
+int smbus_read_byte(u8 device, u8 address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
index 15025702f1..3072b6c547 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
@@ -24,6 +24,7 @@
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include "i82371eb.h"
+#include "i82371eb_smbus.h"
 
 /* TODO: Needed later? */
 static const struct smbus_bus_operations lops_smbus_bus = {
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/i82371eb_smbus.h
index a189425395..54e7906223 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.h
@@ -10,6 +10,9 @@
 #define SMBUS_STATUS_MASK 0x1e
 #define SMBUS_ERROR_FLAG (1<<2)
 
+void enable_smbus(void);
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address);
+
 static inline void smbus_delay(void)
 {
 	outb(0x80, 0x80);
@@ -63,7 +66,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 	return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
 }
 
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
 {
 	unsigned status_register;
 	unsigned byte;