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authorAngel Pons <th3fanbus@gmail.com>2020-01-01 18:05:08 +0100
committerNico Huber <nico.h@gmx.de>2020-01-10 14:49:12 +0000
commit118b18e63af881bc4f1c03914431b2c07c837285 (patch)
tree8b973b98ee17db8e0745ba81ea6dc937f7e11e31 /src
parent9f363fc85aef290d20f7102a16af0df274beadd8 (diff)
downloadcoreboot-118b18e63af881bc4f1c03914431b2c07c837285.tar.xz
mb/**/devicetree.cb: Remove untrue comments
Even if they were corrected, they just rephrase the code. Change-Id: Iebc4e8c9eb0f44f84acf532ad12a5d064075a102 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb1
-rw-r--r--src/mainboard/facebook/monolith/devicetree.cb2
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb1
-rw-r--r--src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb1
-rw-r--r--src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb1
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/devicetree.cb1
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/devicetree.cb1
7 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index bf4bec0e5e..fa94dd9e5b 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -16,7 +16,6 @@
chip soc/intel/skylake
- # Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index b5e3191fcb..85052ec8b8 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -1,6 +1,5 @@
chip soc/intel/skylake
- # Enable deep Sx states
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
@@ -24,7 +23,6 @@ chip soc/intel/skylake
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
- # Enable DPTF
register "dptf_enable" = "0"
# FSP Configuration
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 7d7b58bd34..5d69e52740 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -15,7 +15,6 @@
chip soc/intel/skylake
- # Enable deep Sx states
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index deac4105f1..f69c4822bb 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -8,7 +8,6 @@ chip soc/intel/skylake
register "gpu_pch_backlight_pwm_hz" = "200"
- # Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"
diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
index fd301cd9b3..f5b8b99885 100644
--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
@@ -8,7 +8,6 @@ chip soc/intel/skylake
register "gpu_pch_backlight_pwm_hz" = "200"
- # Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index deb98690f8..b55ef41f2d 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -1,5 +1,4 @@
chip soc/intel/skylake
- # Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index ee7c932dd8..998f3dd366 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -1,6 +1,5 @@
chip soc/intel/skylake
- # Enable deep Sx states
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"