diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-07-24 11:11:03 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-07-24 23:59:51 +0000 |
| commit | 130f266c6e19d5078313fb5f6e29c0a198dbc734 (patch) | |
| tree | 346062da5a4383e6e716e733a6f750e5977a11e8 /src | |
| parent | 695576799bcaa0967bb1af30f65fd38b3532b8bd (diff) | |
| download | coreboot-130f266c6e19d5078313fb5f6e29c0a198dbc734.tar.xz | |
soc/intel/common/block: Add max SPI transaction time-out as 5 sec
Earlier 15ms time-out was kept for SPI transactions which was not
enough for SPI Erase transactions.
Increase the max time-out time to 5 secs which was present in SKL
before common code.
This increase in time-out won't disturb other SPI transactions like
Read, Write or Read Status, since, for those it will come out of
the loop once FDONE bit or FCERR bit is set.
BUG=b:63959637
BRANCH=none
TEST=Built and booted poppy and all SPI transactions succeeded.
Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi_def.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 1262e6aed0..d28f39cdf3 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -150,7 +150,7 @@ /* Programmable values of Bit0(SSMS) of Set STRAP MSG Control (0xF4) Register*/ #define SPIBAR_RESET_CTRL_SSMC 1 /* Set_Strap Mux Select(SSMS) Bit=1*/ -#define SPIBAR_HWSEQ_XFER_TIMEOUT 15 /* 15ms*/ +#define SPIBAR_HWSEQ_XFER_TIMEOUT 5000 /* max 5s*/ void *fast_spi_get_bar(void); |