HWM: Nuvoton W83795G/ADG HWM support

Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans,
they are controled by a separate W83795G Hardware Monitor chip.
This patch adds Nuvoton W83795G/ADG HWM support.

Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/569
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

10 files changed, 356 insertions, 2 deletions

diff --git a/src/drivers/i2c/Kconfig b/src/drivers/i2c/Kconfig
index 91ad025149..09c306b1e6 100644
--- a/src/drivers/i2c/Kconfig
+++ b/src/drivers/i2c/Kconfig
@@ -4,3 +4,4 @@ source src/drivers/i2c/adt7463/Kconfig
 source src/drivers/i2c/i2cmux/Kconfig
 source src/drivers/i2c/i2cmux2/Kconfig
 source src/drivers/i2c/lm63/Kconfig
+source src/drivers/i2c/w83795/Kconfig
diff --git a/src/drivers/i2c/Makefile.inc b/src/drivers/i2c/Makefile.inc
index d462b694a3..97e9729957 100644
--- a/src/drivers/i2c/Makefile.inc
+++ b/src/drivers/i2c/Makefile.inc
@@ -4,3 +4,4 @@ subdirs-y += adt7463
 subdirs-y += i2cmux
 subdirs-y += i2cmux2
 subdirs-y += lm63
+subdirs-y += w83795
diff --git a/src/drivers/i2c/w83795/Kconfig b/src/drivers/i2c/w83795/Kconfig
new file mode 100644
index 0000000000..80856e2b3b
--- /dev/null
+++ b/src/drivers/i2c/w83795/Kconfig
@@ -0,0 +1,2 @@
+config DRIVERS_I2C_W83795
+	bool
diff --git a/src/drivers/i2c/w83795/Makefile.inc b/src/drivers/i2c/w83795/Makefile.inc
new file mode 100644
index 0000000000..708a170b2e
--- /dev/null
+++ b/src/drivers/i2c/w83795/Makefile.inc
@@ -0,0 +1 @@
+driver-$(CONFIG_DRIVERS_I2C_W83795) += w83795.c
diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h
new file mode 100644
index 0000000000..290063682f
--- /dev/null
+++ b/src/drivers/i2c/w83795/chip.h
@@ -0,0 +1,4 @@
+extern struct chip_operations drivers_i2c_w83795_ops;
+
+struct drivers_i2c_w83795_config {
+};
diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c
new file mode 100644
index 0000000000..392471a9a8
--- /dev/null
+++ b/src/drivers/i2c/w83795/w83795.c
@@ -0,0 +1,261 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <device/device.h>
+#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/
+#include "w83795.h"
+
+static u32 w83795_set_bank(u8 bank)
+{
+	return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank);
+}
+
+static u8 w83795_read(u16 reg)
+{
+	u32 ret;
+
+	ret = w83795_set_bank(reg >> 8);
+	if (ret < 0) {
+		printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8);
+		return -1;
+	}
+
+	ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff);
+	return ret;
+}
+
+static u8 w83795_write(u16 reg, u8 value)
+{
+	u32 err;
+
+	err = w83795_set_bank(reg >> 8);
+	if (err < 0) {
+		printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8);
+		return -1;
+	}
+
+	err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value);
+	return err;
+}
+
+/*
+ * Enable Digital Temperature Sensor
+ */
+static void w83795_dts_enable(u8 dts_src)
+{
+	u8 val;
+
+	/* DIS */
+	val = w83795_read(W83795_REG_DTSC);
+	val |= (dts_src & 0x01);
+	w83795_write(W83795_REG_DTSC, val);
+
+	/* DTSE */
+	val = w83795_read(W83795_REG_DTSE);
+	val |= 0xFF;
+	w83795_write(W83795_REG_DTSE, val);
+
+	/* store bank3 regs first before enable DTS */
+
+	/*
+	 * TD/TR1-4 termal diode by default
+	 *  0x00 Disable
+	 *  0x01 thermistors on motherboard
+	 *  0x10 different mode voltage
+	 *  0x11 CPU internal thermal diode output
+	 *
+	 * TR5-6 thermistors by default  TRn
+	 */
+	val = 0x55; /* thermal diode */
+	w83795_write(W83795_REG_TEMP_CTRL2, val);
+
+	/* Enable Digital Temperature Sensor */
+	val = w83795_read(W83795_REG_TEMP_CTRL1);
+	val |= W83795_REG_TEMP_CTRL1_EN_DTS; /* EN_DTS */
+	w83795_write(W83795_REG_TEMP_CTRL1, val);
+}
+
+static void w83795_set_tfmr(w83795_fan_mode_t mode)
+{
+	u8 val;
+	u8 i;
+
+	if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) {
+		val = 0xFF;
+	} else {
+		val = 0x00;
+	}
+
+	for (i = 0; i < 6; i++)
+		w83795_write(W83795_REG_TFMR(i), val);
+}
+
+static u32 w83795_set_fan_mode(w83795_fan_mode_t mode)
+{
+	if (mode == SPEED_CRUISE_MODE) {
+		w83795_write(W83795_REG_FCMS1, 0xFF);
+		printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n");
+	}  else {
+		w83795_write(W83795_REG_FCMS1, 0x00);
+		if (mode == THERMAL_CRUISE_MODE) {
+			w83795_write(W83795_REG_FCMS2, 0x00);
+			printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n");
+		} else if (mode == SMART_FAN_MODE) {
+			w83795_write(W83795_REG_FCMS2, 0x3F);
+			printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n");
+		} else {
+			printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static void w83795_set_tss(void)
+{
+	u8 val;
+
+	val = 0x00;
+	w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */
+	w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */
+	w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */
+}
+
+static void w83795_set_fan(w83795_fan_mode_t mode)
+{
+	u8 i;
+
+	/* select temperature sensor (TSS)*/
+	w83795_set_tss();
+
+	/* select Temperature to Fan mapping Relationships (TFMR)*/
+	w83795_set_tfmr(mode);
+
+	/* set fan output controlled mode (FCMS)*/
+	w83795_set_fan_mode(mode);
+
+	/* Set Critical Temperature to Full Speed all fan (CTFS) */
+	for (i = 0; i < 6; i++) {
+		w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */
+	}
+
+	if (mode == THERMAL_CRUISE_MODE) {
+		/* Set Target Temperature of Temperature Inputs (TTTI) */
+		for (i = 0; i < 6; i++) {
+			w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */
+		}
+	} else if (mode == SMART_FAN_MODE) {
+		/* Set the Relative Register-at SMART FAN IV Control Mode Table */
+		//SFIV TODO
+	}
+
+	/* Set Hystersis of Temperature (HT) */
+	//TODO
+}
+
+static void w83795_init(w83795_fan_mode_t mode, u8 dts_src)
+{
+	u8 i;
+	u8 val;
+
+	if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) {
+		printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n");
+		return;
+	}
+	val = w83795_read(W83795_REG_CONFIG);
+	if ((val & W83795_REG_CONFIG_CONFIG48) == 0)
+		printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n");
+	else if ((val & W83795_REG_CONFIG_CONFIG48) == 1)
+		printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n");
+
+	/* Reset */
+	val |= W83795_REG_CONFIG_INIT;
+	w83795_write(W83795_REG_CONFIG, val);
+
+	/* Fan monitoring setting */
+	val = 0xFF; /* FAN1-FAN8 */
+	w83795_write(W83795_REG_FANIN_CTRL1, val);
+	val = 0x3F; /* FAN9-FAN14 */
+	w83795_write(W83795_REG_FANIN_CTRL2, val);
+
+	/* enable monitoring operations */
+	val = w83795_read(W83795_REG_CONFIG);
+	val |= W83795_REG_CONFIG_START;
+	w83795_write(W83795_REG_CONFIG, val);
+
+	w83795_dts_enable(dts_src);
+	w83795_set_fan(mode);
+
+	printk(BIOS_INFO, "Fan   CTFS(celsius)  TTTI(celsius)\n");
+	for (i = 0; i < 6; i++) {
+		val = w83795_read(W83795_REG_CTFS(i));
+		printk(BIOS_INFO, " %x     %d", i, val);
+		val = w83795_read(W83795_REG_TTTI(i));
+		printk(BIOS_INFO, "             %d\n", val);
+	}
+
+	/* Temperature ReadOut */
+	for (i = 0; i < 9; i++) {
+		val = w83795_read(W83795_REG_DTS(i));
+		printk(BIOS_DEBUG, "DTS%x ReadOut=%x \n", i, val);
+	}
+}
+
+static void w83795_hwm_init(device_t dev)
+{
+	struct device *cpu;
+	struct cpu_info *info;
+
+	info = cpu_info();
+	cpu = info->cpu;
+	if (!cpu)
+		die("CPU: missing cpu device structure");
+
+	if (cpu->vendor == X86_VENDOR_AMD)
+		w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI);
+	else if (cpu->vendor == X86_VENDOR_INTEL)
+		w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_INTEL_PECI);
+	else
+		printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n");
+}
+
+static void w83795_noop(device_t dummy)
+{
+}
+
+static struct device_operations w83795_operations = {
+	.read_resources = w83795_noop,
+	.set_resources = w83795_noop,
+	.enable_resources = w83795_noop,
+	.init = w83795_hwm_init,
+};
+
+static void enable_dev(device_t dev)
+{
+	dev->ops = &w83795_operations;
+}
+
+struct chip_operations drivers_i2c_w83795_ops = {
+	CHIP_NAME("Nuvoton W83795G/ADG Hardware Monitor")
+	.enable_dev = enable_dev,
+};
diff --git a/src/drivers/i2c/w83795/w83795.h b/src/drivers/i2c/w83795/w83795.h
new file mode 100644
index 0000000000..de0a554f5d
--- /dev/null
+++ b/src/drivers/i2c/w83795/w83795.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _W83795_H_
+#define _W83795_H_
+
+#define W83795_DEV			0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */
+
+#define W83795_REG_I2C_ADDR		0xFC
+#define W83795_REG_BANKSEL		0x00
+#define W83795_REG_CONFIG		0x01
+#define W83795_REG_CONFIG_START		0x01
+#define W83795_REG_CONFIG_CONFIG48	0x04
+#define W83795_REG_CONFIG_INIT		0x80
+
+#define W83795_REG_TEMP_CTRL1		0x04 /* Temperature Monitoring Control Register */
+#define W83795_REG_TEMP_CTRL2		0x05 /* Temperature Monitoring Control Register */
+#define W83795_REG_FANIN_CTRL1		0x06
+#define W83795_REG_FANIN_CTRL2		0x07
+#define W83795_REG_TEMP_CTRL1_EN_DTS	0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */
+#define DTS_SRC_INTEL_PECI		(0 << 0)
+#define DTS_SRC_AMD_SBTSI		(1 << 0)
+
+#define W83795_REG_TSS(n)		(0x209 + (n)) /* Temperature Source Selection Register */
+#define W83795_REG_TTTI(n)		(0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */
+#define W83795_REG_CTFS(n)		(0x268 + (n)) /* Critical Temperature to Full Speed all fan */
+#define W83795_REG_HT(n)		(0x270 + (n)) /* Hystersis of Temperature */
+#define W83795_REG_DTSC			0x301 /* Digital Temperature Sensor Configuration */
+
+#define W83795_REG_DTSE			0x302 /* Digital Temperature Sensor Enable */
+#define W83795_REG_DTS(n)		(0x26 + (n))
+#define W83795_REG_VRLSB		0x3C
+
+#define W83795_TEMP_REG_TR1		0x21
+#define W83795_TEMP_REG_TR2		0x22
+#define W83795_TEMP_REG_TR3		0x23
+#define W83795_TEMP_REG_TR4		0x24
+#define W83795_TEMP_REG_TR5		0x1F
+#define W83795_TEMP_REG_TR6		0x20
+
+#define W83795_REG_FCMS1		0x201
+#define W83795_REG_FCMS2		0x208
+#define W83795_REG_TFMR(n)		(0x202 + (n)) /*temperature to fam mappig*/
+#define W83795_REG_DFSP			0x20C
+
+#define W83795_REG_FTSH(n)		(0x240 + (n) * 2)
+#define W83795_REG_FTSL(n)		(0x241 + (n) * 2)
+#define W83795_REG_TFTS			0x250
+
+typedef enum w83795_fan_mode {
+	SPEED_CRUISE_MODE,	///< Fan Speed Cruise mode keeps the fan speed in a specified range
+	THERMAL_CRUISE_MODE,	///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI
+	SMART_FAN_MODE,		///< Smart Fan mode offers 6 slopes to control the fan speed
+	MANUAL_MODE,		///< control manually
+} w83795_fan_mode_t;
+
+#endif
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
index e900ea8399..58f56929ac 100644
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOUTHBRIDGE_AMD_CIMX_SB700
 	select SUPERIO_WINBOND_W83627DHG
 	select SUPERIO_NUVOTON_WPCM450
+	select DRIVERS_I2C_W83795
 	select UDELAY_TSC
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
index 9d77a73463..8ecf96880e 100644
--- a/src/mainboard/supermicro/h8qgi/devicetree.cb
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@@ -84,8 +84,8 @@ chip northbridge/amd/agesa/family15/root_complex
 								irq 0x70 = 0x01 #keyboard
 								irq 0x72 = 0x0C #mouse
 							end
-							#device pnp 2e.6 off #  SPI
-							#end
+							device pnp 2e.6 off #  SPI
+							end
 							device pnp 2e.307 off #  GPIO6
 							end
 							device pnp 2e.8 off #  WDTO#, PLED
@@ -106,6 +106,10 @@ chip northbridge/amd/agesa/family15/root_complex
 							device pnp 2e.c off # PECI, SST
 							end
 						end #superio/winbond/w83627dhg
+						chip drivers/i2c/w83795
+							device pnp 5e on #hwm
+							end
+						end #drivers/i2c/w83795
 					end # LPC
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 3
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index ba8c5e5f6e..d4354fd92f 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -90,6 +90,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x3C);
+	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
+	 * In order to access W83795G/ADG HWM using I2C protocol,
+	 * we select function to SDA, SCL function (or GP33, GP32 function).
+	 */
+	w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
+
 	nb_Ht_Init();
 	post_code(0x3D);
 	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */