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authorZhao, Lijian <lijian.zhao@intel.com>2016-02-01 16:41:59 -0800
committerAaron Durbin <adurbin@chromium.org>2016-04-28 05:46:00 +0200
commit164e8f1d9b9a36ccca2feefa0e2172ac0c3254c3 (patch)
treee442d1a021a4738e32e89cc040b61f41c652525d /src
parent0c85b7f4d7180c9307fd95bb887791d4231397a5 (diff)
downloadcoreboot-164e8f1d9b9a36ccca2feefa0e2172ac0c3254c3.tar.xz
soc/intel/apollolake: Add GPIO devices
Add GPIO controller in ACPI device description. GPIO controller driver is probed in kernel and all the pins in the banks are showing respective values. Change-Id: I0512cfec872113b15fd204ec3b95efeac87f694a Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/14478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/acpi/gpio.asl144
-rw-r--r--src/soc/intel/apollolake/acpi/soc_int.asl1
-rw-r--r--src/soc/intel/apollolake/acpi/southbridge.asl3
3 files changed, 148 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
new file mode 100644
index 0000000000..4bf04428eb
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -0,0 +1,144 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <soc/gpio_defs.h>
+
+scope (\_SB) {
+
+ Device (GPO0)
+ {
+ Name (_ADR, 0)
+ Name (_HID, "INT3452")
+ Name (_CID, "INT3452")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" )
+ Name (_UID, 1)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ {
+ GPIO_BANK_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ ShiftLeft (GPIO_NORTH, 16, Local0)
+ Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ }
+
+ Device (GPO1)
+ {
+ Name (_ADR, 0)
+ Name (_HID, "INT3452")
+ Name (_CID, "INT3452")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" )
+ Name (_UID, 2)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ {
+ GPIO_BANK_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ ShiftLeft (GPIO_NORTHWEST, 16, Local0)
+ Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ }
+
+ Device (GPO2)
+ {
+ Name (_ADR, 0)
+ Name (_HID, "INT3452")
+ Name (_CID, "INT3452")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" )
+ Name (_UID, 3)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ {
+ GPIO_BANK_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ ShiftLeft (GPIO_WEST, 16, Local0)
+ Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ }
+
+ Device (GPO3)
+ {
+ Name (_ADR, 0)
+ Name (_HID, "INT3452")
+ Name (_CID, "INT3452")
+ Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" )
+ Name (_UID, 4)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ {
+ GPIO_BANK_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ ShiftLeft (GPIO_SOUTHWEST, 16, Local0)
+ Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl
index 7db23ee0d7..c7259d0d7c 100644
--- a/src/soc/intel/apollolake/acpi/soc_int.asl
+++ b/src/soc/intel/apollolake/acpi/soc_int.asl
@@ -24,6 +24,7 @@
#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/
#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/
#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/
+#define GPIO_BANK_INT 16
#define NPK_INT 16
#define PIRQA_INT 16
#define PIRQB_INT 17
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 46d701328a..0584439a2a 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -20,3 +20,6 @@
/* PCI IRQ assignment */
#include "pci_irqs.asl"
+
+/* GPIO controller */
+#include "gpio.asl"