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authorFurquan Shaikh <furquan@google.com>2014-08-21 12:52:06 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-03-27 08:03:37 +0100
commit1af7b5ddf116ac1cb3c7acf5a116b60f7a942f4a (patch)
tree57c0e0a4aad6659dee3a6db59229ea379ada0f8b /src
parent4e994c0219a6bba368e8c38dcc914d9c4bb3d339 (diff)
downloadcoreboot-1af7b5ddf116ac1cb3c7acf5a116b60f7a942f4a.tar.xz
arm64: Initialize exception stack
Initialize the exception stack on stage_entry BUG=chrome-os-partner:31515 BRANCH=None TEST=Exception handling works fine Change-Id: I66b4e73e77ad746e891cb2ae6662fbf0531f9d8a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a21d0a432e1742fd8b36b3f8fc7748152f7d74d2 Original-Change-Id: I0b6fb95c660c68fb47a30e905acb910b0e2eafea Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213673 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm64/stage_entry.S12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S
index c18c9cfeaa..4c26f65707 100644
--- a/src/arch/arm64/stage_entry.S
+++ b/src/arch/arm64/stage_entry.S
@@ -55,6 +55,16 @@ ENTRY(arm64_el3_startup)
and x0, x0, x1
msr SCR_EL3, x0
+ /* Initialize SP_EL3 as exception stack */
+ ldr x0, .exception_stack_top
+ cmp x0, #0
+ b.eq 2f
+ msr SPSel, #1
+ isb
+
+ mov sp, x0
+
+ 2:
/* Have stack pointer use SP_EL0. */
msr SPSel, #0
isb
@@ -81,6 +91,8 @@ ENTRY(arm64_el3_startup)
* to the Kconfig option for cpu0. However, this code can be relocated
* and reused to start up secondary cpus.
*/
+ .exception_stack_top:
+ .quad CONFIG_EXCEPTION_STACK_TOP
.stack_top:
.quad _estack
.entry: