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authorKevin Chang <kevin.chang@lcfc.corp-partner.google.com>2020-12-16 11:25:16 +0800
committerHung-Te Lin <hungte@chromium.org>2020-12-24 08:16:28 +0000
commit1cfc3a68e2b60a12bf76cb2f835def40d8cd3fb2 (patch)
treee6b717f7e4b750352eea8b863aca4bb73ec2eefd /src
parent9e2761fe2ba3f9a193885a44fb045be60dc7b2b1 (diff)
downloadcoreboot-1cfc3a68e2b60a12bf76cb2f835def40d8cd3fb2.tar.xz
mb/google/volteer/variant/lindar: Add SSD D3 cold support
This patch add SSD D3 cold support for lindar. BUG=b:172405687 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ie343bbff3bde4ff2a7e89bd384d5661af372b560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/volteer/variants/lindar/overridetree.cb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
index 70e432d55a..d3be955626 100644
--- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
@@ -157,6 +157,14 @@ chip soc/intel/tigerlake
device pnp 0c09.0 on end
end
end
+ device ref pcie_rp9 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A22)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+ register "srcclk_pin" = "0"
+ device generic 0 on end
+ end
+ end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.