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authorAlex Mauer <hawke@hawkesnest.net>2008-09-12 20:39:04 +0000
committerAlex Mauer <hawke@hawkesnest.net>2008-09-12 20:39:04 +0000
commit229c20f3e21e556bd83287e7342f96d2375ae2f4 (patch)
tree31a2c4e0f7dd24e3e6e0e5daafaf81973c628268 /src
parent53bbb0f6b1bd96a7ad8c5cd0d45e0b2705704f6d (diff)
downloadcoreboot-229c20f3e21e556bd83287e7342f96d2375ae2f4.tar.xz
For the jetway jf2/4 series of mainboards:
* change the comment for device f.0 from "IDE" to "SATA" * turn on firewire device a.0 * turn on pata device f.1 * don't turn on the unusable device 10.5 (built-in vt8237 ethernet?) Signed-off-by: Alex Mauer <hawke@hawkesnest.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/jetway/j7f24/Config.lb5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/jetway/j7f24/Config.lb b/src/mainboard/jetway/j7f24/Config.lb
index ce53f7b3f2..f665fdbf44 100644
--- a/src/mainboard/jetway/j7f24/Config.lb
+++ b/src/mainboard/jetway/j7f24/Config.lb
@@ -97,15 +97,16 @@ chip northbridge/via/cn700 # Northbridge
# Both cables are 40pin.
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
- device pci f.0 on end # IDE
register "fn_ctrl_lo" = "0x80"
register "fn_ctrl_hi" = "0x1d"
+ device pci a.0 on end # Firewire
+ device pci f.0 on end # SATA
+ device pci f.1 on end # IDE
device pci 10.0 on end # OHCI
device pci 10.1 on end # OHCI
device pci 10.2 on end # OHCI
device pci 10.3 on end # OHCI
device pci 10.4 on end # EHCI
- device pci 10.5 on end # UDCI
device pci 11.0 on # Southbridge LPC
chip superio/fintek/f71805f # Super I/O
device pnp 2e.0 off # Floppy