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authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-12-04 19:38:12 +0300
committerFelix Held <felix-coreboot@felixheld.de>2019-12-05 15:25:03 +0000
commit2f50d7cd3bac409390b3e3131650a5c5b26a4e0b (patch)
tree14458e942a0107dca34ac41b9de74eed07642c81 /src
parentb1ea707bdaf064ae1d2427e5e3c20d2ab66bf93d (diff)
downloadcoreboot-2f50d7cd3bac409390b3e3131650a5c5b26a4e0b.tar.xz
mb/asrock/h110m: disable CLKREQ to use onboard LAN
The PCH uses the SRCCLKREQ# pin to detect PCIe device in the slot in order to send clock signal to it. However, this logic is not required for the Realtek LAN device, since this chip is soldered to the board and always uses clocking. The chipset can't receive the clock request signal (most likely this pin isn't connected) and doesn't enable the CLK. For this reason, the device is broken during the initialization phase. The patch disables clock request logic for the PCH PCIe port 6 to initialize the onboard LAN device correctly. Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36377 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index bd51e40bf3..bf4bec0e5e 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -219,10 +219,8 @@ chip soc/intel/skylake
# Enable Root port 6(x1) for LAN.
register "PcieRpEnable[5]" = "1"
- # Enable CLKREQ#
- register "PcieRpClkReqSupport[5]" = "1"
- # Use SRCCLKREQ1#
- register "PcieRpClkReqNumber[5]" = "1"
+ # Disable CLKREQ#, since onboard LAN is always present
+ register "PcieRpClkReqSupport[5]" = "0"
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[5]" = "1"
# Enable Latency Tolerance Reporting Mechanism