diff options
| author | Sven Schnelle <svens@stackframe.org> | 2011-05-03 07:55:43 +0000 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-05-03 07:55:43 +0000 |
| commit | 2f81c03d3a0d3183061ca56aecc306995dd648f2 (patch) | |
| tree | 1543282c0dde026af673b59bdeaa56033ea60ae6 /src | |
| parent | 49ae971333408f2a37b9fd6752f6cc9b8fb7f5b4 (diff) | |
| download | coreboot-2f81c03d3a0d3183061ca56aecc306995dd648f2.tar.xz | |
Enable caching for ROM area in model_6ex/cache_as_ram.inc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 0906bc0e5f..02de5ab50f 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -201,7 +201,17 @@ clear_mtrrs: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr |