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authorSridhar Siricilla <sridhar.siricilla@intel.com>2020-11-05 21:36:39 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-11-07 08:56:05 +0000
commit344a1bd43c63dbfeb3cff04e63d531f32242aba4 (patch)
treea6a3f65dcfb8d2264b9b897c81e4e1e2337cc55d /src
parentf2de1e7e19dccb1901c93ff5093360566f6b88e8 (diff)
downloadcoreboot-344a1bd43c63dbfeb3cff04e63d531f32242aba4.tar.xz
mb/intel/adlrvp: Configure GPIOs to enable DMIC
The patch configures GPIO pins to enable DMIC. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
index c7029fc10b..f91b94faf4 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
@@ -224,17 +224,17 @@ static const struct pad_config gpio_table[] = {
/* SNDW1_DATA */
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
/* SNDW2_CLK */
- PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
/* SNDW2_DATA */
- PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
/* SNDW3_CLK */
- PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
/* SNDW3_DATA */
- PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
/* SNDW4_CLK */
- PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
/* SNDW4_DATA */
- PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
/* SMB_CLK */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),