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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-11-24 16:32:05 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-30 08:13:33 +0000
commit3aa17f76044f92dd772cd2833fa8f30031e17f35 (patch)
treeeb2c3d6fcdfb7dd67d0678c688fc904030f54015 /src
parent2fa1cb15de4b03155277ae96c389753690a5e517 (diff)
downloadcoreboot-3aa17f76044f92dd772cd2833fa8f30031e17f35.tar.xz
AGESA,binaryPI: Fix stack location on entry to romstage
For BSP CPU, set up stack location to match the symbol from car.ld. For AP CPUs the stack is located outside _car_region and is currently not accounted for in the linker scripts. Change-Id: I0ec84ae4e73ecca5034f799cdc2a5c1056ad8b74 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/amd/agesa/cache_as_ram.S26
-rw-r--r--src/drivers/amd/agesa/romstage.c12
-rw-r--r--src/include/cpu/amd/car.h1
3 files changed, 27 insertions, 12 deletions
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 4f1cbea574..e86830f5f7 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -22,6 +22,7 @@
*/
#include "gcccar.inc"
+#include <cpu/x86/lapic_def.h>
#include <cpu/x86/post_code.h>
.code32
@@ -36,6 +37,19 @@ _cache_as_ram_setup:
AMD_ENABLE_STACK
+ /*
+ * Set up bootblock stack on BSP.
+ * AMD_ENABLE_STACK macro sets up a stack for BSP at BSP_STACK_BASE_ADDR
+ * which is 0x30000 (_car_region_end), but for C bootblock the stack
+ * begins at _ecar_stack (see arch/x86/car.ld)
+ */
+ mov $LAPIC_BASE_MSR, %ecx
+ rdmsr
+ test $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax
+ jz ap_entry
+
+ mov $_ecar_stack, %esp
+
/* Align the stack. */
and $0xFFFFFFF0, %esp
@@ -47,11 +61,19 @@ _cache_as_ram_setup:
pushl %eax
call romstage_main
- /* Should never see this postcode */
- post_code(0xae)
+ /* Never reached. */
stop:
+ post_code(POST_DEAD_CODE)
hlt
jmp stop
+ap_entry:
+ /* Align the stack for call to ap_romstage_main() */
+ and $0xfffffff0, %esp
+ call ap_romstage_main
+
+ /* Never reached. */
+ jmp stop
+
_cache_as_ram_setup_end:
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 8460035de4..571397fdb3 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -39,7 +39,7 @@ static void fill_sysinfo(struct sysinfo *cb)
agesa_set_interface(cb);
}
-static void bsp_romstage_main(void)
+asmlinkage void romstage_main(unsigned long bist)
{
struct postcar_frame pcf;
struct sysinfo romstage_state;
@@ -99,7 +99,7 @@ static void bsp_romstage_main(void)
/* We do not return. */
}
-static void __noreturn ap_romstage_main(void)
+asmlinkage void ap_romstage_main(void)
{
struct sysinfo romstage_state;
struct sysinfo *cb = &romstage_state;
@@ -116,11 +116,3 @@ static void __noreturn ap_romstage_main(void)
/* Not reached. */
halt();
}
-
-asmlinkage void romstage_main(unsigned long bist)
-{
- if (boot_cpu())
- bsp_romstage_main();
- else
- ap_romstage_main();
-}
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index 7e2fccd80f..f57ea82ad0 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -4,5 +4,6 @@
#include <arch/cpu.h>
asmlinkage void romstage_main(unsigned long bist);
+asmlinkage void ap_romstage_main(void);
#endif