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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-03-27 22:06:30 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:09:19 +0000 |
| commit | 3b9d995ecb99063adc2c79bb3c2e73de72499e01 (patch) | |
| tree | 4f287743c1e9d35562231e6214c00861ed907ca5 /src | |
| parent | 5fcfbe14818e4a4cb1111c759e183195607e0a91 (diff) | |
| download | coreboot-3b9d995ecb99063adc2c79bb3c2e73de72499e01.tar.xz | |
mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
Update UPD IIO bifurcation at run-time according to different Riser
cards. For detail please reference
Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types.
With the engineering build FSP, it can only configure IIO for
one socket so my local test needs to remove all socket1 elements
from tp_iio_bifur_table.
This change relies on [1] and need to add GPP_C15 and GPP_C16 to
early_gpio_table for gpio configuration in bootblock.
[1] https://review.coreboot.org/c/coreboot/+/39427/
Tested=OCP Tioga Pass can see socket0 IIO being updated with
an engineering build FSP.
Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/ocp/tiogapass/romstage.c | 23 | ||||
| -rw-r--r-- | src/mainboard/ocp/tiogapass/skxsp_tp_iio.h | 13 |
2 files changed, 35 insertions, 1 deletions
diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 8f9806f250..e4a188d35d 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -16,10 +16,29 @@ #include <fsp/api.h> #include <FspmUpd.h> #include <soc/romstage.h> +#include <string.h> +#include <gpio.h> +#include <soc/lewisburg_pch_gpio_defs.h> #include "skxsp_tp_gpio.h" #include "skxsp_tp_iio.h" +static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; + +static void oem_update_iio(FSPM_UPD *mupd) +{ + /* Read GPIO to decide IIO bifurcation at run-time. */ + int slot_config0 = gpio_get(GPP_C15); + int slot_config1 = gpio_get(GPP_C16); + + /* It's a single side 3 slots riser card, to tell which AICs are on each slot requires + reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation + accordingly is left for future work. */ + if (!slot_config0 && slot_config1) + mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation + = IIO_BIFURCATE_xxx8xxx8; +} + /* * Configure GPIO depend on platform */ @@ -32,8 +51,9 @@ static void mainboard_config_gpios(FSPM_UPD *mupd) static void mainboard_config_iio(FSPM_UPD *mupd) { + memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = - (UPD_IIO_BIFURCATION_DATA_ENTRY *) tp_iio_bifur_table; + (UPD_IIO_BIFURCATION_DATA_ENTRY *) iio_table_buf; mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_bifur_table); @@ -49,6 +69,7 @@ static void mainboard_config_iio(FSPM_UPD *mupd) mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00; mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00; + oem_update_iio(mupd); } void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h index 403702035c..d436e885a4 100644 --- a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h +++ b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h @@ -19,6 +19,19 @@ #include <FspmUpd.h> #include <soc/pci_devs.h> +enum tp_iio_bifur_table_index { + Skt0_Iou0 = 0, + Skt0_Iou1, + Skt0_Iou2, + Skt0_Mcp0, + Skt0_Mcp1, + Skt1_Iou0, + Skt1_Iou1, + Skt1_Iou2, + Skt1_Mcp0, + Skt1_Mcp1 +}; + /* * Standard Tioga Pass Iio Bifurcation Table * This is SS 2x16 config. As documented in OCP TP spec, there are |