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authorIru Cai <mytbk920423@gmail.com>2020-10-06 23:00:23 +0800
committerIru Cai <mytbk920423@gmail.com>2020-12-28 21:26:39 +0800
commit3f51905aed39a0fd45a1068881011a8cf0326565 (patch)
tree6cfd8b9f1cf9c30e004796b8ce959af9615cc155 /src
parent5fc74d8d1180d53f6e5ade15528284b073f223d3 (diff)
downloadcoreboot-3f51905aed39a0fd45a1068881011a8cf0326565.tar.xz
[WIP] mb/hp: Add HP ProBook 640 G1
Generate code from autoport. It boots to Arch Linux in a USB disk from SeaBIOS payload. This board doesn't have HP Sure Start enabled, so we can use all the flash regions, and relocate the EC firmware with CB:41393. Change-Id: I07f433784292e3765bde3736414ff0eae525a046 Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/hp/probook_640_g1/Kconfig42
-rw-r--r--src/mainboard/hp/probook_640_g1/Kconfig.name2
-rw-r--r--src/mainboard/hp/probook_640_g1/Makefile.inc3
-rw-r--r--src/mainboard/hp/probook_640_g1/acpi/ec.asl3
-rw-r--r--src/mainboard/hp/probook_640_g1/acpi/platform.asl14
-rw-r--r--src/mainboard/hp/probook_640_g1/acpi/superio.asl3
-rw-r--r--src/mainboard/hp/probook_640_g1/acpi_tables.c15
-rw-r--r--src/mainboard/hp/probook_640_g1/board_info.txt7
-rw-r--r--src/mainboard/hp/probook_640_g1/bootblock.c18
-rw-r--r--src/mainboard/hp/probook_640_g1/devicetree.cb86
-rw-r--r--src/mainboard/hp/probook_640_g1/dsdt.asl27
-rw-r--r--src/mainboard/hp/probook_640_g1/gma-mainboard.ads22
-rw-r--r--src/mainboard/hp/probook_640_g1/gpio.c228
-rw-r--r--src/mainboard/hp/probook_640_g1/hda_verb.c25
-rw-r--r--src/mainboard/hp/probook_640_g1/mainboard.c14
-rw-r--r--src/mainboard/hp/probook_640_g1/romstage.c56
16 files changed, 565 insertions, 0 deletions
diff --git a/src/mainboard/hp/probook_640_g1/Kconfig b/src/mainboard/hp/probook_640_g1/Kconfig
new file mode 100644
index 0000000000..d0e8b65404
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/Kconfig
@@ -0,0 +1,42 @@
+if BOARD_HP_PROBOOK_640_G1
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_16384
+ select EC_HP_KBC1126
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_HASWELL
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_LYNXPOINT
+ select SUPERIO_SMSC_LPC47N217
+ select SYSTEM_TYPE_LAPTOP
+
+config MAINBOARD_DIR
+ string
+ default "hp/probook_640_g1"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "HP ProBook 640 G1"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0416.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0416"
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 1
+
+config EC_HP_KBC1126_ECFW_IN_CBFS
+ bool
+ default n
+
+endif
diff --git a/src/mainboard/hp/probook_640_g1/Kconfig.name b/src/mainboard/hp/probook_640_g1/Kconfig.name
new file mode 100644
index 0000000000..f809069fbb
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_HP_PROBOOK_640_G1
+ bool "ProBook 640 G1"
diff --git a/src/mainboard/hp/probook_640_g1/Makefile.inc b/src/mainboard/hp/probook_640_g1/Makefile.inc
new file mode 100644
index 0000000000..fa23791fc1
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/Makefile.inc
@@ -0,0 +1,3 @@
+bootblock-y += bootblock.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/hp/probook_640_g1/acpi/ec.asl b/src/mainboard/hp/probook_640_g1/acpi/ec.asl
new file mode 100644
index 0000000000..baa17a4181
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/hp/kbc1126/acpi/ec.asl>
diff --git a/src/mainboard/hp/probook_640_g1/acpi/platform.asl b/src/mainboard/hp/probook_640_g1/acpi/platform.asl
new file mode 100644
index 0000000000..8023ae826c
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/acpi/platform.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK,1)
+{
+ \_SB.PCI0.LPCB.EC0.ACPI = 1
+ \_SB.PCI0.LPCB.EC0.SLPT = 0
+
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ \_SB.PCI0.LPCB.EC0.SLPT = Arg0
+}
diff --git a/src/mainboard/hp/probook_640_g1/acpi/superio.asl b/src/mainboard/hp/probook_640_g1/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/hp/probook_640_g1/acpi_tables.c b/src/mainboard/hp/probook_640_g1/acpi_tables.c
new file mode 100644
index 0000000000..f9ac854b2e
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/acpi_tables.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <southbridge/intel/lynxpoint/nvs.h>
+
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/hp/probook_640_g1/board_info.txt b/src/mainboard/hp/probook_640_g1/board_info.txt
new file mode 100644
index 0000000000..7f58055212
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/board_info.txt
@@ -0,0 +1,7 @@
+Category: laptop
+Board URL: https://support.hp.com/us-en/product/hp-probook-640-g1-notebook-pc/5405392/
+ROM protocol: SPI
+ROM package: SOIC-8
+ROM socketed: n
+Flashrom support: y
+Release year: 2014
diff --git a/src/mainboard/hp/probook_640_g1/bootblock.c b/src/mainboard/hp/probook_640_g1/bootblock.c
new file mode 100644
index 0000000000..b5b6d43d8a
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/bootblock.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <superio/smsc/lpc47n217/lpc47n217.h>
+#include <ec/hp/kbc1126/ec.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
+
+void mainboard_config_superio(void)
+{
+ lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ kbc1126_enter_conf();
+ kbc1126_mailbox_init();
+ kbc1126_kbc_init();
+ kbc1126_ec_init();
+ kbc1126_pm1_init();
+ kbc1126_exit_conf();
+}
diff --git a/src/mainboard/hp/probook_640_g1/devicetree.cb b/src/mainboard/hp/probook_640_g1/devicetree.cb
new file mode 100644
index 0000000000..5804283217
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/devicetree.cb
@@ -0,0 +1,86 @@
+chip northbridge/intel/haswell
+ register "ec_present" = "true"
+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+ register "gpu_ddi_e_connected" = "1"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_power_backlight_off_delay" = "1"
+ register "gpu_panel_power_backlight_on_delay" = "1"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "500"
+ register "gpu_panel_power_up_delay" = "2000"
+ register "gpu_pch_backlight_pwm_hz" = "200"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/haswell
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0x0 on
+ subsystemid 0x103c 0x1993 inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+ device pci 03.0 on end # Mini-HD audio
+
+ chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0201"
+ register "gen2_dec" = "0x000c0101"
+ register "gen4_dec" = "0x000402e9"
+ register "gpi6_routing" = "2"
+ register "sata_ahci" = "1"
+ register "sata_port0_gen3_dtle" = "0x7"
+ # 0(HDD), 1(ODD), 5(M.2)
+ register "sata_port_map" = "0x37"
+ device pci 14.0 on end # xHCI Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 on end # PCIe Port #7, WLAN
+ device pci 1c.7 on end # PCIe Port #8, Card Reader
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1f.0 on # LPC bridge
+ chip ec/hp/kbc1126
+ register "ec_data_port" = "0x62"
+ register "ec_cmd_port" = "0x66"
+ register "ec_ctrl_reg" = "0x81"
+ register "ec_fan_ctrl_value" = "0x5f"
+ device pnp ff.1 off end
+ end
+ chip superio/smsc/lpc47n217
+ device pnp 4e.3 on # Parallel
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 4e.4 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 off end # COM2
+ end
+ end
+ device pci 1f.2 on end # SATA Controller (AHCI)
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller (Legacy)
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/hp/probook_640_g1/dsdt.asl b/src/mainboard/hp/probook_640_g1/dsdt.asl
new file mode 100644
index 0000000000..f030e72471
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/haswell/acpi/haswell.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/lynxpoint/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/hp/probook_640_g1/gma-mainboard.ads b/src/mainboard/hp/probook_640_g1/gma-mainboard.ads
new file mode 100644
index 0000000000..fd2a5d5bdb
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/gma-mainboard.ads
@@ -0,0 +1,22 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ eDP,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/probook_640_g1/gpio.c b/src/mainboard/hp/probook_640_g1/gpio.c
new file mode 100644
index 0000000000..629117afa0
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/gpio.c
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_OUTPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio2 = GPIO_LEVEL_LOW,
+ .gpio11 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio3 = GPIO_INVERT,
+ .gpio4 = GPIO_INVERT,
+ .gpio6 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio9 = GPIO_INVERT,
+ .gpio10 = GPIO_INVERT,
+ .gpio19 = GPIO_INVERT,
+ .gpio21 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_GPIO,
+ .gpio41 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_GPIO,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+ .gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio56 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+ .gpio61 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_OUTPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_OUTPUT,
+ .gpio71 = GPIO_DIR_OUTPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio68 = GPIO_LEVEL_HIGH,
+ .gpio70 = GPIO_LEVEL_HIGH,
+ .gpio71 = GPIO_LEVEL_HIGH,
+ .gpio74 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/hp/probook_640_g1/hda_verb.c b/src/mainboard/hp/probook_640_g1/hda_verb.c
new file mode 100644
index 0000000000..5c0f943e5a
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/hda_verb.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x00000000, /* Codec Vendor / Device ID: */
+ 0x00000000, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x00000000),
+ AZALIA_PIN_CFG(0, 0x0a, 0x21011030),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0),
+ AZALIA_PIN_CFG(0, 0x0f, 0x2181102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x40f000f0),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30140),
+ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x40f000f0),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/probook_640_g1/mainboard.c b/src/mainboard/hp/probook_640_g1/mainboard.c
new file mode 100644
index 0000000000..98cc8110cc
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/mainboard.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/hp/probook_640_g1/romstage.c b/src/mainboard/hp/probook_640_g1/romstage.c
new file mode 100644
index 0000000000..4dd5db7142
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/romstage.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_rcba(void)
+{
+ RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA);
+ RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC);
+ RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA);
+ RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD);
+ RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD);
+ RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD);
+ RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
+ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
+}
+
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+ spd_map[0] = 0xa0;
+ spd_map[2] = 0xa4;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
+ /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */
+ /* Length, Enable, OCn#, Location */
+ { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, /* dock */
+ { 0x0080, 1, 0, USB_PORT_BACK_PANEL }, /* right */
+ { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* right */
+ { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* left */
+ { 0x0110, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0080, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, /* webcam */
+ { 0x0080, 1, 3, USB_PORT_DOCK },
+ { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* left */
+ { 0x0110, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, /* M.2 */
+ { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, /* WLAN */
+ { 0x0110, 1, 6, USB_PORT_BACK_PANEL },
+ { 0x0080, 1, 6, USB_PORT_DOCK },
+ };
+ struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
+ { 1, 0 },
+ { 1, 0 },
+ { 1, 1 },
+ { 1, 1 },
+ { 1, 2 },
+ { 0, 2 },
+ };
+ memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
+ memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
+}