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authorCaveh Jalali <caveh@chromium.org>2018-09-06 19:55:21 -0700
committerFurquan Shaikh <furquan@google.com>2018-09-07 23:40:08 +0000
commit41979d862a972375d6800afdf2b8b52d408fd220 (patch)
tree0c215e5ebbb14fd92e59b89092148a3258b5cda4 /src
parentdce4d465a6eed58c7dc99b5b3267eea751738b01 (diff)
downloadcoreboot-41979d862a972375d6800afdf2b8b52d408fd220.tar.xz
mb/google/poppy/variants/atlas: enable NVMe
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and clock#4. BUG=b:113369699 TEST=booted on atlas Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb18
-rw-r--r--src/mainboard/google/poppy/variants/atlas/gpio.c4
2 files changed, 18 insertions, 4 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index c96081cd87..968faefaf1 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -147,7 +147,7 @@ chip soc/intel/skylake
.dc_loadline = 441,
}"
- # PCIe Root port 1 with SRCCLKREQ1#
+ # PCIe Root port 1 with SRCCLKREQ1# (WLAN)
register "PcieRpEnable[0]" = "1"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
@@ -155,6 +155,20 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
+ # PCIe Root port 5 (NVMe)
+ # PcieRpEnable: Enable root port
+ # PcieRpClkReqSupport: Enable CLKREQ#
+ # PcieRpClkReqNumber: Uses SRCCLKREQ4#
+ # PcieRpClkSrcNumber: Uses CLKOUT_PCIE_4
+ # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
+ # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "4"
+ register "PcieRpClkSrcNumber[4]" = "4"
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ register "PcieRpLtrEnable[4]" = "1"
+
# USB 2.0
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty
@@ -329,7 +343,7 @@ chip soc/intel/skylake
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.4 on end # PCI Express Port 5 (NVMe)
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c
index 5f1a1f5628..f82976e2d4 100644
--- a/src/mainboard/google/poppy/variants/atlas/gpio.c
+++ b/src/mainboard/google/poppy/variants/atlas/gpio.c
@@ -78,8 +78,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NC(GPP_B7),
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
PAD_CFG_GPO(GPP_B8, 0, RSMRST),
- /* B9 : SRCCLKREQ4# ==> NC */
- PAD_CFG_NC(GPP_B9),
+ /* B9 : SRCCLKREQ4# ==> NVME_PCIE_CLKREQ_L */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* B10 : SRCCLKREQ5# ==> NC */
PAD_CFG_NC(GPP_B10),
/* B11 : EXT_PWR_GATE# ==> NC */