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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-11-09 12:06:19 +1100
committerPatrick Georgi <pgeorgi@google.com>2014-11-09 12:26:34 +0100
commit48b6b97eb4388e68a5ba30e7df3baded7dc37a03 (patch)
tree82b80004c152ec45f3c687f0e7dcb7a109338f00 /src
parent27cf24727c26874cbe61734d01074f6da077d1b9 (diff)
downloadcoreboot-48b6b97eb4388e68a5ba30e7df3baded7dc37a03.tar.xz
src: Too many terminators ';;' at end of stmts, stop Skynet
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/rambi/mainboard_smi.c2
-rw-r--r--src/soc/intel/baytrail/refcode.c2
-rw-r--r--src/soc/intel/broadwell/refcode.c2
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c2
-rw-r--r--src/vendorcode/amd/cimx/sb800/DISPATCHER.c2
-rw-r--r--src/vendorcode/amd/pi/00730F01/Lib/amdlib.c2
7 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
index f2bb7e97ad..bd7646899f 100644
--- a/src/mainboard/google/rambi/mainboard_smi.c
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -139,7 +139,7 @@ int mainboard_smi_apmc(uint8_t apmc)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
- google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
return 0;
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index 92731bb4fa..e85521889e 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -90,7 +90,7 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
c->magic = RAMSTAGE_CACHE_MAGIC;
c->entry_point = (uint32_t)rsl->entry;
c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry);
- c->size = cbmem_entry_size(rsl->cbmem_entry);;
+ c->size = cbmem_entry_size(rsl->cbmem_entry);
printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n",
&c->program[0], c->size);
diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c
index 3d2f8b5713..a745101535 100644
--- a/src/soc/intel/broadwell/refcode.c
+++ b/src/soc/intel/broadwell/refcode.c
@@ -95,7 +95,7 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
c->magic = RAMSTAGE_CACHE_MAGIC;
c->entry_point = (uint32_t)rsl->entry;
c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry);
- c->size = cbmem_entry_size(rsl->cbmem_entry);;
+ c->size = cbmem_entry_size(rsl->cbmem_entry);
printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n",
&c->program[0], c->size);
diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
index 9646e6d3b9..a2c424ab87 100644
--- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
@@ -837,7 +837,7 @@ LibAmdPciWrite (
LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
}
//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
- //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
+ //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
} else {
// Setup the MMIO address
diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
index 99a28b1c08..d0e66b9fc9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
@@ -842,7 +842,7 @@ LibAmdPciWrite (
LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
}
//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
- //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
+ //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
} else {
// Setup the MMIO address
diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
index d3a6c3a7b4..84bbccb7c3 100644
--- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
+++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
@@ -159,7 +159,7 @@ AmdSbDispatcher (
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
- sbECfancontrolservice((AMDSBCFG*)pConfig);;
+ sbECfancontrolservice((AMDSBCFG*)pConfig);
}
#endif
return Status;
diff --git a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
index 54e0d77bf2..f2e6b91748 100644
--- a/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
+++ b/src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
@@ -865,7 +865,7 @@ LibAmdPciWrite (
LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
}
//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
- //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
+ //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
} else {
// Setup the MMIO address