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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-09-04 13:08:25 -0600
committerMartin Roth <martinroth@google.com>2018-09-07 14:51:31 +0000
commit4b0f6fa156a9a474adb2e1e296ed990458ecdf26 (patch)
tree379e0cefc6dbb1dd0a3fdcf86e5cce678820aa92 /src
parentbb7f1b41e7cf04f81c9ed37b1e275495fa4397a9 (diff)
downloadcoreboot-4b0f6fa156a9a474adb2e1e296ed990458ecdf26.tar.xz
amd/stoneyridge: Adjust memory map for reserved
Carve out memory to be reported to the OS as reserved. This makes room for a region usable for Boot Error Record Table information. The BERT region reserved size is larger than likely requried, however the SMM region's base must be on a boundary matching the granularity of its size. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I0958f6b6bab3fe9dae36c83e1fd9ae6ed0290a18 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28474 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/ramtop.c22
1 files changed, 20 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index 24386edba3..e9a0e530c5 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -23,6 +23,7 @@
#include <cpu/amd/amdfam15.h>
#include <cbmem.h>
#include <stage_cache.h>
+#include <arch/bert_storage.h>
#include <soc/northbridge.h>
#include <soc/southbridge.h>
@@ -36,6 +37,22 @@ uintptr_t restore_top_of_low_cacheable(void)
return biosram_read32(BIOSRAM_CBMEM_TOP);
}
+#if IS_ENABLED(CONFIG_ACPI_BERT)
+/* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */
+#define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE
+#else
+#define BERT_REGION_MAX_SIZE 0
+#endif
+
+void bert_reserved_region(void **start, size_t *size)
+{
+ if (IS_ENABLED(CONFIG_ACPI_BERT))
+ *start = cbmem_top();
+ else
+ start = NULL;
+ *size = BERT_REGION_MAX_SIZE;
+}
+
void *cbmem_top(void)
{
msr_t tom = rdmsr(TOP_MEM);
@@ -45,12 +62,13 @@ void *cbmem_top(void)
else
/* 8MB alignment to keep MTRR usage low */
return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
- - CONFIG_SMM_TSEG_SIZE, 8*MiB);
+ - CONFIG_SMM_TSEG_SIZE
+ - BERT_REGION_MAX_SIZE, 8*MiB);
}
static uintptr_t smm_region_start(void)
{
- return (uintptr_t)cbmem_top();
+ return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE;
}
static size_t smm_region_size(void)