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authorAaron Durbin <adurbin@chromium.org>2014-09-24 09:13:14 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-03-28 08:45:05 +0100
commit4f9150bf23c3f49d02e85129c7067e05bc9f8d23 (patch)
treea2d9dc02da6c9c142cbf9f31e1d9b267510604ce /src
parent852b50c87f1fb907c31a1a20fd55db4a64096ccc (diff)
downloadcoreboot-4f9150bf23c3f49d02e85129c7067e05bc9f8d23.tar.xz
tegra132: measure romstage timings
Measure the MTS load time, MTS initialization time, and the ramstage verification/load time. BUG=None BRANCH=None TEST=Booted and noted timings. Change-Id: I1eb1e3a73316a3fa76ef8e73314bedde34c6c582 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b5b34a3abd388359b7d1cba5a858e4e5a402b476 Original-Change-Id: I71119689182e86406d5052f007908152d41e9092 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219715 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9103 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/nvidia/tegra132/ccplex.c8
-rw-r--r--src/soc/nvidia/tegra132/romstage.c7
2 files changed, 13 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index 9c0cc5c726..b183e5d1e1 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -67,7 +67,7 @@ static int ccplex_start(void)
}
}
- printk(BIOS_DEBUG, "MTS handshake took %ld us.\n",
+ printk(BIOS_DEBUG, "MTS handshake took %ld usecs.\n",
stopwatch_duration_usecs(&sw));
return 0;
@@ -78,6 +78,8 @@ int ccplex_load_mts(void)
struct cbfs_file file;
ssize_t offset;
size_t nread;
+ struct stopwatch sw;
+
/*
* MTS location is hard coded to this magic address. The hardware will
* take the MTS from this location and place it in the final resting
@@ -86,6 +88,7 @@ int ccplex_load_mts(void)
void * const mts = (void *)(uintptr_t)MTS_LOAD_ADDRESS;
struct cbfs_media *media = CBFS_DEFAULT_MEDIA;
+ stopwatch_init(&sw);
offset = cbfs_locate_file(media, &file, MTS_FILE_NAME);
if (offset < 0) {
printk(BIOS_DEBUG, "MTS file not found: %s\n", MTS_FILE_NAME);
@@ -101,7 +104,8 @@ int ccplex_load_mts(void)
return -1;
}
- printk(BIOS_DEBUG, "MTS: %zu bytes loaded @ %p\n", nread, mts);
+ printk(BIOS_DEBUG, "MTS: %zu bytes loaded @ %p in %ld usecs.\n",
+ nread, mts, stopwatch_duration_usecs(&sw));
return ccplex_start();
}
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 3fd3266f35..9051a81e6f 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -22,6 +22,7 @@
#include <cbmem.h>
#include <console/cbmem_console.h>
#include <console/console.h>
+#include <timer.h>
#include <arch/exception.h>
#include <soc/addressmap.h>
@@ -40,6 +41,9 @@ void __attribute__((weak)) romstage_mainboard_init(void)
static void *load_ramstage(void)
{
void *entry;
+ struct stopwatch sw;
+
+ stopwatch_init(&sw);
/*
* This platform does not need to cache a loaded ramstage nor do we
* go down this path on resume. Therefore, no romstage_handoff is
@@ -48,6 +52,9 @@ static void *load_ramstage(void)
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
CONFIG_CBFS_PREFIX "/ramstage");
+ printk(BIOS_DEBUG, "Ramstage load time: %ld usecs.\n",
+ stopwatch_duration_usecs(&sw));
+
return entry;
}