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authorPeter Lemenkov <lemenkov@gmail.com>2019-01-10 12:19:01 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-14 11:57:25 +0000
commit522a1b526b31c66aed2d75e99dd810dc5a136bbf (patch)
treefd30402b5c542428059d75b0f1f3355d0124d417 /src
parente23245517bed9befc41bbc8c571e05782a95d5fe (diff)
downloadcoreboot-522a1b526b31c66aed2d75e99dd810dc5a136bbf.tar.xz
mb/lenovo/[xtz]60: Introduce and use RCBA64 macro
Change-Id: I85ca631dfb01acb92dd1ac38dff07215114cab8c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/t60/romstage.c6
-rw-r--r--src/mainboard/lenovo/x60/romstage.c6
-rw-r--r--src/mainboard/lenovo/z61t/romstage.c6
-rw-r--r--src/southbridge/intel/common/rcba.h1
4 files changed, 7 insertions, 12 deletions
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 72dd8b42c3..3017357235 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -100,12 +100,10 @@ static void rcba_config(void)
RCBA32(FD) |= FD_INTLAN;
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
- RCBA32(IOTR0) = 0x0000fe01;
- RCBA32(IOTR0+4) = 0x00020001;
+ RCBA64(IOTR0) = 0x000200010000fe01ULL;
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
- RCBA32(IOTR3) = 0x000c0801;
- RCBA32(IOTR3+4) = 0x000200f0;
+ RCBA64(IOTR3) = 0x000200f0000c0801ULL;
}
static void early_ich7_init(void)
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 8943f975af..6f66c88c96 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -99,12 +99,10 @@ static void rcba_config(void)
RCBA32(FD) |= FD_INTLAN;
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
- RCBA32(IOTR0) = 0x0000fe01;
- RCBA32(IOTR0+4) = 0x00020001;
+ RCBA64(IOTR0) = 0x000200010000fe01ULL;
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
- RCBA32(IOTR3) = 0x000c0801;
- RCBA32(IOTR3+4) = 0x000200f0;
+ RCBA64(IOTR3) = 0x000200f0000c0801ULL;
}
static void early_ich7_init(void)
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index 966d0e5759..6eceaeb77d 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -100,12 +100,10 @@ static void rcba_config(void)
RCBA32(FD) |= FD_INTLAN;
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
- RCBA32(IOTR0) = 0x0000fe01;
- RCBA32(IOTR0+4) = 0x00020001;
+ RCBA64(IOTR0) = 0x000200010000fe01ULL;
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
- RCBA32(IOTR3) = 0x000c0801;
- RCBA32(IOTR3+4) = 0x000200f0;
+ RCBA64(IOTR3) = 0x000200f0000c0801ULL;
}
static void early_ich7_init(void)
diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h
index e7482f9bdb..225cd26086 100644
--- a/src/southbridge/intel/common/rcba.h
+++ b/src/southbridge/intel/common/rcba.h
@@ -28,6 +28,7 @@
#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))
#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))
#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))
+#define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + x)))
#define RCBA_AND_OR(bits, x, and, or) \
(RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))