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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-04 16:41:27 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-04 13:48:13 +0100
commit536a44390d719a92cda72dbe76cea38c8c62a92b (patch)
treea9ebed9c5ed48d6a48037776322c7d82b4c82ee0 /src
parentb8f05d4faab11a7b726963dc3821a682281eea02 (diff)
downloadcoreboot-536a44390d719a92cda72dbe76cea38c8c62a92b.tar.xz
superio/smsc/lpc47b397: Use link-time symbols over .c inclusion
Change-Id: I344f2a8d2ae5f6f3fa04d79773ee1c59de69e425 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8079 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/sunw/ultra40/Kconfig1
-rw-r--r--src/mainboard/sunw/ultra40/romstage.c2
-rw-r--r--src/mainboard/tyan/s2895/romstage.c2
-rw-r--r--src/superio/smsc/lpc47b397/Makefile.inc1
-rw-r--r--src/superio/smsc/lpc47b397/early_serial.c4
-rw-r--r--src/superio/smsc/lpc47b397/lpc47b397.h11
6 files changed, 15 insertions, 6 deletions
diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig
index 3fb559123e..8f3ff2a825 100644
--- a/src/mainboard/sunw/ultra40/Kconfig
+++ b/src/mainboard/sunw/ultra40/Kconfig
@@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_AMD_SOCKET_940
select NORTHBRIDGE_AMD_AMDK8
select SOUTHBRIDGE_NVIDIA_CK804
+ select SUPERIO_SMSC_LPC47B397
select SUPERIO_SMSC_LPC47M10X
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index 7c112da98f..99d0dfb7be 100644
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -16,7 +16,7 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/smsc/lpc47b397/early_serial.c"
+#include <superio/smsc/lpc47b397/lpc47b397.h>
#include "cpu/x86/bist.h"
#include "superio/smsc/lpc47b397/early_gpio.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index 4f0e552ed4..0e42f76974 100644
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -15,7 +15,7 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/smsc/lpc47b397/early_serial.c"
+#include <superio/smsc/lpc47b397/lpc47b397.h>
#include "superio/smsc/lpc47b397/early_gpio.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
diff --git a/src/superio/smsc/lpc47b397/Makefile.inc b/src/superio/smsc/lpc47b397/Makefile.inc
index 30101cf52e..d25febc98e 100644
--- a/src/superio/smsc/lpc47b397/Makefile.inc
+++ b/src/superio/smsc/lpc47b397/Makefile.inc
@@ -20,4 +20,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c
diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c
index 953cd4bbb1..047145e7f3 100644
--- a/src/superio/smsc/lpc47b397/early_serial.c
+++ b/src/superio/smsc/lpc47b397/early_serial.c
@@ -21,6 +21,8 @@
*/
#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
#include "lpc47b397.h"
static void pnp_enter_conf_state(pnp_devfn_t dev)
@@ -35,7 +37,7 @@ static void pnp_exit_conf_state(pnp_devfn_t dev)
outb(0xaa, port);
}
-static void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase)
+void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
diff --git a/src/superio/smsc/lpc47b397/lpc47b397.h b/src/superio/smsc/lpc47b397/lpc47b397.h
index 310084a857..996b7cd078 100644
--- a/src/superio/smsc/lpc47b397/lpc47b397.h
+++ b/src/superio/smsc/lpc47b397/lpc47b397.h
@@ -20,8 +20,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef SUPERIO_SMSC_LPC47B397_LPC47B397_H
-#define SUPERIO_SMSC_LPC47B397_LPC47B397_H
+#ifndef SUPERIO_SMSC_LPC47B397_H
+#define SUPERIO_SMSC_LPC47B397_H
#define LPC47B397_FDC 0 /* Floppy */
#define LPC47B397_PP 3 /* Parallel Port */
@@ -31,4 +31,9 @@
#define LPC47B397_HWM 8 /* HW Monitor */
#define LPC47B397_RT 10 /* Runtime reg*/
-#endif
+#include <arch/io.h>
+#include <stdint.h>
+
+void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase);
+
+#endif /* SUPERIO_SMSC_LPC47B397_H */