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authorFurquan Shaikh <furquan@google.com>2018-10-16 11:54:37 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-10-18 12:46:12 +0000
commit585210ad587675067d59e8f408be4d2f5a860acf (patch)
tree2775080efacaedf9752f157a11c2a63dcc29aa5a /src
parent9706359fd8077e4027f6c8c8586bc40bdbb3a3f7 (diff)
downloadcoreboot-585210ad587675067d59e8f408be4d2f5a860acf.tar.xz
drivers/intel/fsp*: Use newly added post codes for memory param prep
This change replaces use of post codes 0x34 and 0x36 in fsp drivers to instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to search from where these post codes are generated during boot flow. Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init to make it consistent with fsp1_1 memory init. Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/intel/fsp1_1/raminit.c4
-rw-r--r--src/drivers/intel/fsp1_1/romstage.c2
-rw-r--r--src/drivers/intel/fsp2_0/memory_init.c4
3 files changed, 6 insertions, 4 deletions
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 407a0b6093..bca9f71f19 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -64,7 +64,7 @@ void raminit(struct romstage_params *params)
* set to NULL. This indicates that the FSP code will use the UPD
* region in the FSP binary.
*/
- post_code(0x34);
+ post_code(POST_MEM_PREINIT_PREP_START);
fsp_header = params->chipset_context;
vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
fsp_header->ImageBase);
@@ -103,7 +103,7 @@ void raminit(struct romstage_params *params)
if (IS_ENABLED(CONFIG_MMA))
setup_mma(&memory_init_params);
- post_code(0x36);
+ post_code(POST_MEM_PREINIT_PREP_END);
/* Display the UPD data */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index b239d86480..8e8c24c96c 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -344,7 +344,7 @@ __weak int mrc_cache_stash_data(int type, uint32_t version,
/* Transition RAM from off or self-refresh to active */
__weak void raminit(struct romstage_params *params)
{
- post_code(0x34);
+ post_code(POST_MEM_PREINIT_PREP_START);
die("ERROR - No RAM initialization specified!\n");
}
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index dc37eaaf1b..1026c7982d 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -273,7 +273,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
FSPM_ARCH_UPD *arch_upd;
uint32_t fsp_version;
- post_code(0x34);
+ post_code(POST_MEM_PREINIT_PREP_START);
fsp_version = fsp_memory_settings_version(hdr);
@@ -301,6 +301,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
if (IS_ENABLED(CONFIG_MMA))
setup_mma(&fspm_upd.FspmConfig);
+ post_code(POST_MEM_PREINIT_PREP_END);
+
/* Call FspMemoryInit */
fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);