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| author | Greg Watson <jarrah@users.sourceforge.net> | 2004-06-03 16:55:24 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2004-06-03 16:55:24 +0000 |
| commit | 5b2565a6df7d9f8f9b6354be797ee926586618af (patch) | |
| tree | 48dffac0626fb0199c6fdab389f55808e0333fc3 /src | |
| parent | f78ba9dfa635580eaa7a49421c397b939529f1b5 (diff) | |
| download | coreboot-5b2565a6df7d9f8f9b6354be797ee926586618af.tar.xz | |
fixup
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/totalimpact/briq/Config.lb | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb index 74a36eb3ab..1a1c66c5a0 100644 --- a/src/mainboard/totalimpact/briq/Config.lb +++ b/src/mainboard/totalimpact/briq/Config.lb @@ -15,12 +15,6 @@ default PCIC0_CFGADDR=0xff508000 default PCIC0_CFGDATA=0xff508010 ## -## Set IDE control registers -## -default PNP_CFGADDR=0x1f0 -default PNP_CFGDATA=0x1f1 - -## ## Set UART base address ## default TTYS0_BASE=0x3f8 @@ -28,8 +22,13 @@ default TTYS0_BASE=0x3f8 ## ## Early board initialization, called from ppc_main() ## -initobject init.c -driver pci_bridge.c +initobject init.o +initobject clock.o + +## +## Stage 2 timer support +## +object clock.o arch ppc end @@ -43,6 +42,7 @@ end ## ## Include the secondary Configuration files ## +northbridge ibm/cpc710 end southbridge winbond/w83c553 end ## |