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| author | Raul E Rangel <rrangel@chromium.org> | 2020-06-12 11:41:16 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-19 20:34:06 +0000 |
| commit | 5e29c0ef8e310dd6e8dcfef6596c4268b9995169 (patch) | |
| tree | 91dcc7796007b2f5c1d3cee2b1ba9b703640cc7d /src | |
| parent | 51e0fd91d5d73c168e572622f91d0197a8ec031b (diff) | |
| download | coreboot-5e29c0ef8e310dd6e8dcfef6596c4268b9995169.tar.xz | |
mb/google/zork: Disable UART 1, 2 and 3
We don't use these on zork, so lets save the power.
BUG=b:153001807
TEST=Boot OS and make sure UART 1, 2 and 3 are not probed and remain
powered off.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2fadeba779b66ec2fb13951b9487118ef0737a94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb index 664e379035..18c3783e83 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -187,4 +187,8 @@ chip soc/amd/picasso end end + device mmio 0xfedca000 off end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + end # chip soc/amd/picasso |