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authorShunqian Zheng <zhengsq@rock-chips.com>2016-08-10 04:45:50 +0800
committerMartin Roth <martinroth@google.com>2016-08-16 21:19:00 +0200
commit5fa08f3c0f34fec0fa3bf0a34425c96932d62931 (patch)
treeac5c1d33f12a4235da841df55c563d3f216219bf /src
parente4cc4733ebd4c6fc77de5f0a9963e9a938e57e5d (diff)
downloadcoreboot-5fa08f3c0f34fec0fa3bf0a34425c96932d62931.tar.xz
Revert "rockchip: rk3399: enable sdhci clk for emmc"
This reverts commit 462e1413 ("rockchip: rk3399: enable sdhci clk for emmc") Enabling this clock in coreboot is no longer needed as it's handled in the kernel driver now. BUG=chrome-os-partner:52873 TEST=boot from usb/sdcard and check there is /dev/mmcblk0 BRANCH=none Change-Id: I92cf51f175fe56a09ab9329b29a27c77ef4328e1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5707d1269a253dabf825be120d1f9348ffaab6d0 Original-Change-Id: I8bca870c663d8ce8fac5daaaaf8225489f22ed13 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/367421 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16152 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/gru/mainboard.c3
-rw-r--r--src/soc/rockchip/rk3399/Makefile.inc1
-rw-r--r--src/soc/rockchip/rk3399/emmc.c50
-rw-r--r--src/soc/rockchip/rk3399/include/soc/emmc.h16
4 files changed, 0 insertions, 70 deletions
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index e2205e0e0f..8a6cda203d 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -22,7 +22,6 @@
#include <soc/bl31_plat_params.h>
#include <soc/clock.h>
#include <soc/display.h>
-#include <soc/emmc.h>
#include <soc/grf.h>
#include <soc/i2c.h>
#include <soc/usb.h>
@@ -42,8 +41,6 @@ static void configure_emmc(void)
write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
rkclk_configure_emmc();
-
- enable_emmc_clk();
}
static void register_reset_to_bl31(void)
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 768367ec22..3bfc05e956 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -65,7 +65,6 @@ ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
ramstage-y += clock.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/edp.c
-ramstage-y += emmc.c
ramstage-y += ../common/gpio.c
ramstage-y += gpio.c
ramstage-y += ../common/i2c.c
diff --git a/src/soc/rockchip/rk3399/emmc.c b/src/soc/rockchip/rk3399/emmc.c
deleted file mode 100644
index b8519f7796..0000000000
--- a/src/soc/rockchip/rk3399/emmc.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <delay.h>
-#include <soc/addressmap.h>
-#include <soc/emmc.h>
-
-#define SDHCI_CLOCK_CONTROL 0x2c
-#define SDHCI_CLOCK_CARD_EN 0x0004
-#define SDHCI_CLOCK_INT_STABLE 0x0002
-#define SDHCI_CLOCK_INT_EN 0x0001
-
-/* TODO(crosbug.com/p/52873): We actually don't need to set clk for
- * emmc once kernel fix it's bug.
- */
-void enable_emmc_clk(void)
-{
- int timeout, clk;
-
- write32((void *)(EMMC_BASE + SDHCI_CLOCK_CONTROL), SDHCI_CLOCK_INT_EN);
-
- /* Wait max 20 ms */
- timeout = 20;
- while (!((clk = read32((void *)(EMMC_BASE + SDHCI_CLOCK_CONTROL)))
- & SDHCI_CLOCK_INT_STABLE)) {
- if (timeout == 0) {
- printk(BIOS_ERR, "Internal clock never stabilised.\n");
- return;
- }
- timeout--;
- udelay(1000);
- }
-
- clk |= SDHCI_CLOCK_CARD_EN;
- write32((void *)(EMMC_BASE + SDHCI_CLOCK_CONTROL), clk);
-}
diff --git a/src/soc/rockchip/rk3399/include/soc/emmc.h b/src/soc/rockchip/rk3399/include/soc/emmc.h
deleted file mode 100644
index 0d29d9e138..0000000000
--- a/src/soc/rockchip/rk3399/include/soc/emmc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-void enable_emmc_clk(void);