diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-02-19 22:49:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-26 17:07:05 +0000 |
| commit | 6130ad26b7fd2f2945d04aca10a5c5961e7d4edc (patch) | |
| tree | 4cdd71f02a23f735ad3dd2e31913c1409b9d5acc /src | |
| parent | 6424ac923264f5c3ef03a357c11001f052fc609e (diff) | |
| download | coreboot-6130ad26b7fd2f2945d04aca10a5c5961e7d4edc.tar.xz | |
mb/google/dedede: Update GPE configuration
WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is
routed to GPP_C12 GPIO. Update the GPE configuration accordingly.
BUG=None
TEST=Build the mainboard.
Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 346a3096b6..37bb8f23c2 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -11,13 +11,14 @@ chip soc/intel/tigerlake # - GPP_B3 - TRACKPAD_INT_ODL # - GPP_B4 - H1_AP_INT_ODL # DW1 is used by: - # - GPP_D3 - WLAN_PCIE_WAKE_ODL + # - GPP_C12 - AP_PEN_DET_ODL # DW2 is used by: - # - GPP_H16 - WWAN_HOST_WAKE + # - GPP_D0 - WWAN_HOST_WAKE + # - GPP_D3 - WLAN_PCIE_WAKE_ODL # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" - register "pmc_gpe0_dw2" = "GPP_H" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_D" # USB Port Configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 |