summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorPaul Fagerburg <pfagerburg@chromium.org>2019-06-13 14:38:08 -0600
committerFurquan Shaikh <furquan@google.com>2019-06-13 22:29:10 +0000
commit6440cb6945df740648ab3193a7d2025527b84522 (patch)
tree1216bfbd2a1eaaf8700941bbf16c566af0389f3d /src
parent6ff848aaf811789460f7bf6f0f89f71aa7fe8bee (diff)
downloadcoreboot-6440cb6945df740648ab3193a7d2025527b84522.tar.xz
mb/google/hatch/variants/helios: Use LPDDR3 memory
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays for mapping SoC DQS pins to LPDDR3 pins. BRANCH=none BUG=b:133455595 TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage` Ensure the firmware builds without error. Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/variants/helios/Makefile.inc10
-rw-r--r--src/mainboard/google/hatch/variants/helios/memory.c68
2 files changed, 72 insertions, 6 deletions
diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc
index cf6ee5ac97..ddafa3297f 100644
--- a/src/mainboard/google/hatch/variants/helios/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc
@@ -12,9 +12,7 @@
## GNU General Public License for more details.
##
-SPD_SOURCES = 4G_2400 # 0b000
-SPD_SOURCES += empty_ddr4 # 0b001
-SPD_SOURCES += 8G_2400 # 0b010
-SPD_SOURCES += 8G_2666 # 0b011
-SPD_SOURCES += 16G_2400 # 0b100
-SPD_SOURCES += 16G_2666 # 0b101
+SPD_SOURCES = LP_8G_2133 # 0b0000
+SPD_SOURCES += LP_16G_2133 # 0b0001
+
+romstage-y += memory.c
diff --git a/src/mainboard/google/hatch/variants/helios/memory.c b/src/mainboard/google/hatch/variants/helios/memory.c
new file mode 100644
index 0000000000..64b4cac8d0
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/helios/memory.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <soc/cnl_memcfg_init.h>
+#include <string.h>
+
+static const struct cnl_mb_cfg baseboard_memcfg = {
+ /*
+ * The dqs_map arrays map the SoC pins to the lpddr3 pins
+ * for both channels.
+ *
+ * "The index of the array is CPU byte number, the values are DRAM byte
+ * numbers." - doc #573387
+ *
+ * the index = pin number on SoC
+ * the value = pin number on lpddr3 part
+ */
+ .dqs_map[DDR_CH0] = {4, 7, 5, 6, 0, 3, 2, 1},
+ .dqs_map[DDR_CH1] = {0, 3, 2, 1, 4, 7, 6, 5},
+
+ .dq_map[DDR_CH0] = {
+ {0xf0, 0xf},
+ {0x0, 0xf},
+ {0xf0, 0xf},
+ {0xf0, 0x0},
+ {0xff, 0x0},
+ {0xff, 0x0}
+ },
+ .dq_map[DDR_CH1] = {
+ {0xf, 0xf0},
+ {0x0, 0xf0},
+ {0xf, 0xf0},
+ {0xf, 0x0},
+ {0xff, 0x0},
+ {0xff, 0x0}
+ },
+
+ /* Helios uses 200, 80.6 and 162 rcomp resistors */
+ .rcomp_resistor = {200, 81, 162},
+
+ /* Helios Rcomp target values */
+ .rcomp_targets = {100, 40, 40, 23, 40},
+
+ /* Set CaVref config to 0 for LPDDR3 */
+ .vref_ca_config = 0,
+
+ /* Disable Early Command Training */
+ .ect = 0,
+};
+
+void variant_memory_params(struct cnl_mb_cfg *bcfg)
+{
+ memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
+}