summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-02-05 19:08:03 +0100
committerArthur Heymans <arthur@aheymans.xyz>2018-04-10 09:30:21 +0000
commit67031a565b3179fa5a28282fc2e24b47d16003e8 (patch)
treed56eaf320fcdc2b2940a24d77c20077fb970951c /src
parent64f0bcb6b0c4ee0fb55e6e600a48a1c61d2e97ef (diff)
downloadcoreboot-67031a565b3179fa5a28282fc2e24b47d16003e8.tar.xz
cpu/intel/sandybridge: Put stage cache into TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. The code is mostly copied from src/cpu/intel/haswell. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/model_206ax/Kconfig10
-rw-r--r--src/cpu/intel/model_206ax/Makefile.inc3
-rw-r--r--src/cpu/intel/model_206ax/model_206ax.h22
-rw-r--r--src/cpu/intel/model_206ax/stage_cache.c28
-rw-r--r--src/cpu/intel/smm/gen1/smmrelocate.c4
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h3
6 files changed, 69 insertions, 1 deletions
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index f16b11962c..b30cfa10c2 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -22,6 +22,7 @@ config CPU_SPECIFIC_OPTIONS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config BOOTBLOCK_CPU_INIT
string
@@ -35,4 +36,13 @@ config SMM_TSEG_SIZE
hex
default 0x800000
+config SMM_RESERVED_SIZE
+ hex
+ default 0x100000
+
+# Intel Enhanced Debug region must be 4MB
+config IED_REGION_SIZE
+ hex
+ default 0x400000
+
endif
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 7516e9d246..1e04554655 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -11,6 +11,9 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 594dde143c..962b8302eb 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -92,6 +92,28 @@
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
+/*
+ * Region of SMM space is reserved for multipurpose use. It falls below
+ * the IED region and above the SMM handler.
+ */
+#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
+#define RESERVED_SMM_OFFSET \
+ (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
+
+/* Sanity check config options. */
+#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
+# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
+#endif
+#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
+# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
+#endif
+#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
+# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
+#endif
+#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)
+# error "CONFIG_IED_REGION_SIZE is not a power of 2"
+#endif
+
#ifdef __SMM__
/* Lock MSRs */
void intel_model_206ax_finalize_smm(void);
diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c
new file mode 100644
index 0000000000..26dc5e03f9
--- /dev/null
+++ b/src/cpu/intel/model_206ax/stage_cache.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <stage_cache.h>
+#include "model_206ax.h"
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ /*
+ * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ * The top of RAM is defined to be the TSEG base address.
+ */
+ *size = RESERVED_SMM_SIZE;
+ *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET);
+}
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index da43de09fd..e80fa31489 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -132,6 +132,10 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
params->ied_base = tsegmb + params->smram_size;
params->ied_size = tseg_size - params->smram_size;
+ /* Adjust available SMM handler memory size. */
+ if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM))
+ params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
+
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index a3b4faad1d..46ebfc3df0 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -40,7 +40,8 @@
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
/* Intel Enhanced Debug region must be 4MB */
-#define IED_SIZE 0x400000
+
+#define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */