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authorFurquan Shaikh <furquan@google.com>2020-05-16 21:44:51 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-20 00:35:17 +0000
commit6dc858a01ffceb897b597607f2004b9aad2f0ae7 (patch)
tree6dd61bfabfae8700e36ae91def78f5cc2e2815a5 /src
parent01750ef8d725895f984c0ae373bab83a925130f0 (diff)
downloadcoreboot-6dc858a01ffceb897b597607f2004b9aad2f0ae7.tar.xz
soc/intel/broadwell: Update systemagent.asl to ASL2.0 syntax
This change updates systemagent.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for auron. Change-Id: I479bb6cb7ed4c9265325c7c8621f03454f21f467 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/broadwell/acpi/systemagent.asl14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl
index c73322ff81..74a25c15fb 100644
--- a/src/soc/intel/broadwell/acpi/systemagent.asl
+++ b/src/soc/intel/broadwell/acpi/systemagent.asl
@@ -147,18 +147,18 @@ Method (_CRS, 0, Serialized)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM
- Store (^MCHC.TLUD, Local0)
- Store (^MCHC.MEBA, Local1)
+ Local0 = ^MCHC.TLUD
+ Local1 = ^MCHC.MEBA
// Check if ME base is equal
- If (LEqual (Local0, Local1)) {
+ If (Local0 == Local1) {
// Use Top Of Memory instead
- Store (^MCHC.TOM, Local0)
+ Local0 = ^MCHC.TOM
}
- Store (Local0, PMIN)
- Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
- Add(Subtract(PMAX, PMIN), 1, PLEN)
+ PMIN = Local0
+ PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
+ PLEN = (PMAX - PMIN) + 1
Return (MCRS)
}