- Ensure every copy of Options.lb uses:

  CROSS_COMPILE
  CC
  HOSTCC
  OBJCOPY


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

29 files changed, 234 insertions, 142 deletions

diff --git a/src/mainboard/Iwill/DK8S2/Options.lb b/src/mainboard/Iwill/DK8S2/Options.lb
index 848d1c833b..91fb272e86 100644
--- a/src/mainboard/Iwill/DK8S2/Options.lb
+++ b/src/mainboard/Iwill/DK8S2/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,6 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE=524288
@@ -161,7 +163,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-#default CC="gcc"
+#default CC="$(CROSS_COMPILE)gcc -m32"
 #default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/Iwill/DK8X/Options.lb b/src/mainboard/Iwill/DK8X/Options.lb
index aae3d6cfd9..2904cccf43 100644
--- a/src/mainboard/Iwill/DK8X/Options.lb
+++ b/src/mainboard/Iwill/DK8X/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,6 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE=524288
@@ -160,7 +162,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-#default CC="gcc"
+#default CC="$(CROSS_COMPILE)gcc -m32"
 #default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/amd/quartet/Options.lb b/src/mainboard/amd/quartet/Options.lb
index 77e54aa3aa..2de7258e12 100644
--- a/src/mainboard/amd/quartet/Options.lb
+++ b/src/mainboard/amd/quartet/Options.lb
@@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -43,6 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
 uses MAXIMUM_CONSOLE_LOGLEVEL
 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 
 ###
@@ -157,7 +159,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc -m32"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c
index 6a3b2194e7..748e0d72ea 100644
--- a/src/mainboard/amd/quartet/auto.c
+++ b/src/mainboard/amd/quartet/auto.c
@@ -154,7 +154,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
-#include "resourcemap.c"	/* quartet does not want the default */
+/* quartet does not want the default */
+#include "resourcemap.c"
 
 #define RC0 ((1<<1)<<8)
 #define RC1 ((1<<2)<<8)
diff --git a/src/mainboard/amd/serenade/Options.lb b/src/mainboard/amd/serenade/Options.lb
index 4c4cfb432b..37fd3ea508 100644
--- a/src/mainboard/amd/serenade/Options.lb
+++ b/src/mainboard/amd/serenade/Options.lb
@@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -43,7 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
 uses MAXIMUM_CONSOLE_LOGLEVEL
 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -157,7 +158,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc -m32"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/amd/solo/Options.lb b/src/mainboard/amd/solo/Options.lb
index 998215d6c6..905fea2df5 100644
--- a/src/mainboard/amd/solo/Options.lb
+++ b/src/mainboard/amd/solo/Options.lb
@@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -43,6 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
 uses MAXIMUM_CONSOLE_LOGLEVEL
 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 
 ###
@@ -157,7 +159,8 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc -m32"
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb
index 8eb01b384d..f669ba9ec2 100644
--- a/src/mainboard/arima/hdama/Options.lb
+++ b/src/mainboard/arima/hdama/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,6 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -163,7 +165,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/densitron/dpx114/Options.lb b/src/mainboard/densitron/dpx114/Options.lb
index ae0756ec04..0b48b69260 100644
--- a/src/mainboard/densitron/dpx114/Options.lb
+++ b/src/mainboard/densitron/dpx114/Options.lb
@@ -27,6 +27,10 @@ uses _RAMBASE
 uses XIP_ROM_SIZE
 uses XIP_ROM_BASE
 uses HAVE_MP_TABLE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -89,4 +93,10 @@ default _RAMBASE = 0x00004000
 
 default CONFIG_ROM_STREAM     = 1
 
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
 end
diff --git a/src/mainboard/digitallogic/adl855pc/Options.lb b/src/mainboard/digitallogic/adl855pc/Options.lb
index dddfdb5541..f9cd639044 100644
--- a/src/mainboard/digitallogic/adl855pc/Options.lb
+++ b/src/mainboard/digitallogic/adl855pc/Options.lb
@@ -27,6 +27,10 @@ uses _RAMBASE
 uses XIP_ROM_SIZE
 uses XIP_ROM_BASE
 uses HAVE_MP_TABLE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -90,6 +94,12 @@ default _RAMBASE = 0x00004000
 
 default CONFIG_ROM_STREAM     = 1
 
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
 end
 
 
diff --git a/src/mainboard/embeddedplanet/ep405pc/Config.lb b/src/mainboard/embeddedplanet/ep405pc/Config.lb
index 38708daac1..4b76162e17 100644
--- a/src/mainboard/embeddedplanet/ep405pc/Config.lb
+++ b/src/mainboard/embeddedplanet/ep405pc/Config.lb
@@ -2,33 +2,6 @@
 ## Config file for the Embedded Planet EP405PC Computing Engine
 ##
 
-uses PCIC0_CFGADDR 
-uses PCIC0_CFGDATA 
-uses ISA_IO_BASE 
-uses ISA_MEM_BASE 
-uses TTYS0_BASE 
-uses _IO_BASE 
-
-##
-## Set PCI configuration register addresses
-##
-default PCIC0_CFGADDR=0xeec00000
-default PCIC0_CFGDATA=0xeec00004
-
-##
-## Set PCI/ISA I/O and memory base address
-##
-default ISA_IO_BASE=0xe8000000
-default ISA_MEM_BASE=0x80000000
-default _IO_BASE=ISA_IO_BASE
-
-##
-## HACK ALERT: the UART0 registers are not in the PCI I/O address space
-## but both IDE and UART use the same routines for I/O (inb/outb). To get 
-## around this we set TTYSO_BASE to the difference between the two.
-##
-default TTYS0_BASE=0xef600300-ISA_IO_BASE
-
 ##
 ## Early board initialization, called from ppc_main()
 ##
diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb
new file mode 100644
index 0000000000..9acea4955f
--- /dev/null
+++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb
@@ -0,0 +1,35 @@
+##
+## Config file for the Embedded Planet EP405PC Computing Engine
+##
+
+uses PCIC0_CFGADDR 
+uses PCIC0_CFGDATA 
+uses ISA_IO_BASE 
+uses ISA_MEM_BASE 
+uses TTYS0_BASE 
+uses _IO_BASE 
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+
+##
+## Set PCI configuration register addresses
+##
+default PCIC0_CFGADDR=0xeec00000
+default PCIC0_CFGDATA=0xeec00004
+
+##
+## Set PCI/ISA I/O and memory base address
+##
+default ISA_IO_BASE=0xe8000000
+default ISA_MEM_BASE=0x80000000
+default _IO_BASE=ISA_IO_BASE
+
+##
+## HACK ALERT: the UART0 registers are not in the PCI I/O address space
+## but both IDE and UART use the same routines for I/O (inb/outb). To get 
+## around this we set TTYSO_BASE to the difference between the two.
+##
+default TTYS0_BASE=0xef600300-ISA_IO_BASE
+
diff --git a/src/mainboard/emulation/qemu-i386/Options.lb b/src/mainboard/emulation/qemu-i386/Options.lb
index 0d0023ff8e..9047dc6000 100644
--- a/src/mainboard/emulation/qemu-i386/Options.lb
+++ b/src/mainboard/emulation/qemu-i386/Options.lb
@@ -34,8 +34,6 @@ uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -45,6 +43,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -159,7 +161,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc -m32"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/ibm/e325/Options.lb b/src/mainboard/ibm/e325/Options.lb
index 7a00b5b150..9e46555e63 100644
--- a/src/mainboard/ibm/e325/Options.lb
+++ b/src/mainboard/ibm/e325/Options.lb
@@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -43,6 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
 uses MAXIMUM_CONSOLE_LOGLEVEL
 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 
 ###
@@ -159,7 +161,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc -m32"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/motorola/sandpoint/Config.lb b/src/mainboard/motorola/sandpoint/Config.lb
index 711ddb2da8..f33ce4bede 100644
--- a/src/mainboard/motorola/sandpoint/Config.lb
+++ b/src/mainboard/motorola/sandpoint/Config.lb
@@ -2,29 +2,6 @@
 ## Config file for the Motorola Sandpoint III development system.
 ## Note that this has only been tested with the Altimus 7410 PMC.
 ##
-uses CONFIG_SANDPOINT_ALTIMUS
-uses CONFIG_SANDPOINT_TALUS
-uses CONFIG_SANDPOINT_UNITY
-uses CONFIG_SANDPOINT_VALIS
-uses CONFIG_SANDPOINT_GYRUS
-uses ISA_IO_BASE
-uses ISA_MEM_BASE
-uses PCIC0_CFGADDR
-uses PCIC0_CFGDATA
-uses PNP_CFGADDR
-uses PNP_CFGDATA
-uses _IO_BASE
-
-##
-## Set memory map
-##
-default ISA_IO_BASE=0xfe000000
-default ISA_MEM_BASE=0xfd000000
-default PCIC0_CFGADDR=0xfec00000
-default PCIC0_CFGDATA=0xfee00000
-default PNP_CFGADDR=0x15c
-default PNP_CFGDATA=0x15d
-default _IO_BASE=ISA_IO_BASE
 
 ##
 ## Early board initialization, called from ppc_main()
diff --git a/src/mainboard/motorola/sandpoint/Options.lb b/src/mainboard/motorola/sandpoint/Options.lb
new file mode 100644
index 0000000000..5ca5007883
--- /dev/null
+++ b/src/mainboard/motorola/sandpoint/Options.lb
@@ -0,0 +1,27 @@
+uses CONFIG_SANDPOINT_ALTIMUS
+uses CONFIG_SANDPOINT_TALUS
+uses CONFIG_SANDPOINT_UNITY
+uses CONFIG_SANDPOINT_VALIS
+uses CONFIG_SANDPOINT_GYRUS
+uses ISA_IO_BASE
+uses ISA_MEM_BASE
+uses PCIC0_CFGADDR
+uses PCIC0_CFGDATA
+uses PNP_CFGADDR
+uses PNP_CFGDATA
+uses _IO_BASE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+
+##
+## Set memory map
+##
+default ISA_IO_BASE=0xfe000000
+default ISA_MEM_BASE=0xfd000000
+default PCIC0_CFGADDR=0xfec00000
+default PCIC0_CFGDATA=0xfee00000
+default PNP_CFGADDR=0x15c
+default PNP_CFGDATA=0x15d
+default _IO_BASE=ISA_IO_BASE
diff --git a/src/mainboard/newisys/khepri/Options.lb b/src/mainboard/newisys/khepri/Options.lb
index 1ae4aa4d46..a7f8f61e67 100644
--- a/src/mainboard/newisys/khepri/Options.lb
+++ b/src/mainboard/newisys/khepri/Options.lb
@@ -34,8 +34,6 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -43,7 +41,10 @@ uses DEFAULT_CONSOLE_LOGLEVEL
 uses MAXIMUM_CONSOLE_LOGLEVEL
 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
-
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -157,7 +158,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc -m32"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb
index 6c54d85120..943018d025 100644
--- a/src/mainboard/totalimpact/briq/Config.lb
+++ b/src/mainboard/totalimpact/briq/Config.lb
@@ -2,34 +2,6 @@
 ## Config file for the Total Impact briQ
 ##
 
-uses TTYS0_DIV
-uses TTYS0_BASE
-uses CONFIG_BRIQ_750FX
-uses CONFIG_BRIQ_7400
-uses ISA_IO_BASE
-uses ISA_MEM_BASE
-uses PCIC0_CFGADDR
-uses PCIC0_CFGDATA
-uses _IO_BASE
-
-##
-## Set memory map
-##
-default ISA_IO_BASE=0x80000000
-default ISA_MEM_BASE=0xc0000000
-default PCIC0_CFGADDR=0xff5f8000
-default PCIC0_CFGDATA=0xff5f8010
-default _IO_BASE=ISA_IO_BASE
-
-##
-## The briQ uses weird clocking, 4 = 115200
-##
-default TTYS0_DIV=4
-##
-## Set UART base address
-##
-default TTYS0_BASE=0x3f8
-
 ##
 ## Early board initialization, called from ppc_main()
 ##
diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb
new file mode 100644
index 0000000000..37bfa24c72
--- /dev/null
+++ b/src/mainboard/totalimpact/briq/Options.lb
@@ -0,0 +1,35 @@
+##
+## Config file for the Total Impact briQ
+##
+
+uses TTYS0_DIV
+uses TTYS0_BASE
+uses CONFIG_BRIQ_750FX
+uses CONFIG_BRIQ_7400
+uses ISA_IO_BASE
+uses ISA_MEM_BASE
+uses PCIC0_CFGADDR
+uses PCIC0_CFGDATA
+uses _IO_BASE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+
+##
+## Set memory map
+##
+default ISA_IO_BASE=0x80000000
+default ISA_MEM_BASE=0xc0000000
+default PCIC0_CFGADDR=0xff5f8000
+default PCIC0_CFGDATA=0xff5f8010
+default _IO_BASE=ISA_IO_BASE
+
+##
+## The briQ uses weird clocking, 4 = 115200
+##
+default TTYS0_DIV=4
+##
+## Set UART base address
+##
+default TTYS0_BASE=0x3f8
diff --git a/src/mainboard/tyan/s2735/Options.lb b/src/mainboard/tyan/s2735/Options.lb
index 655ba4323d..617dfa8650 100644
--- a/src/mainboard/tyan/s2735/Options.lb
+++ b/src/mainboard/tyan/s2735/Options.lb
@@ -35,8 +35,6 @@ uses MAINBOARD_VENDOR
 uses MAINBOARD
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,6 +45,10 @@ uses CONFIG_CONSOLE_SERIAL8250
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -169,7 +171,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/tyan/s2850/Options.lb b/src/mainboard/tyan/s2850/Options.lb
index 4c0dae6875..8e4573789a 100644
--- a/src/mainboard/tyan/s2850/Options.lb
+++ b/src/mainboard/tyan/s2850/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,6 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -162,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/tyan/s2875/Options.lb b/src/mainboard/tyan/s2875/Options.lb
index 103232a5a0..94cc228f6b 100644
--- a/src/mainboard/tyan/s2875/Options.lb
+++ b/src/mainboard/tyan/s2875/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb
index dd95fe7acd..ebef35b617 100644
--- a/src/mainboard/tyan/s2880/Options.lb
+++ b/src/mainboard/tyan/s2880/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb
index e65f53c9b1..93d08bced8 100644
--- a/src/mainboard/tyan/s2881/Options.lb
+++ b/src/mainboard/tyan/s2881/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb
index 14c643d6f5..e26a593d79 100644
--- a/src/mainboard/tyan/s2882/Options.lb
+++ b/src/mainboard/tyan/s2882/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb
index 520fde347c..5c4d79ea52 100644
--- a/src/mainboard/tyan/s2885/Options.lb
+++ b/src/mainboard/tyan/s2885/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,7 +45,11 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -163,7 +165,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb
index f13961fbde..ef3301c1d1 100644
--- a/src/mainboard/tyan/s4880/Options.lb
+++ b/src/mainboard/tyan/s4880/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb
index 2ee7c1b25b..a4a8cb3ffd 100644
--- a/src/mainboard/tyan/s4882/Options.lb
+++ b/src/mainboard/tyan/s4882/Options.lb
@@ -36,8 +36,6 @@ uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
-uses CC
-uses HOSTCC
 uses TTYS0_BAUD
 uses TTYS0_BASE
 uses TTYS0_LCS
@@ -47,7 +45,10 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
-
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ###
 ### Build options
@@ -163,7 +164,7 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="gcc"
+default CC="$(CROSS_COMPILE)gcc -m32"
 default HOSTCC="gcc"
 
 ##
diff --git a/src/mainboard/via/epia-m/Options.lb b/src/mainboard/via/epia-m/Options.lb
index 83f0e59be0..9756d21fe3 100644
--- a/src/mainboard/via/epia-m/Options.lb
+++ b/src/mainboard/via/epia-m/Options.lb
@@ -28,6 +28,10 @@ uses XIP_ROM_SIZE
 uses XIP_ROM_BASE
 uses HAVE_MP_TABLE
 uses HAVE_ACPI_TABLES
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -90,5 +94,12 @@ default _RAMBASE = 0x00004000
 
 default CONFIG_ROM_STREAM     = 1
 
+##
+## The default compiler
+##
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
 end
 
diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb
index 5d5e28fc3e..71ffcb110a 100644
--- a/src/mainboard/via/epia/Options.lb
+++ b/src/mainboard/via/epia/Options.lb
@@ -27,6 +27,10 @@ uses _RAMBASE
 uses XIP_ROM_SIZE
 uses XIP_ROM_BASE
 uses HAVE_MP_TABLE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -90,5 +94,13 @@ default _RAMBASE = 0x00004000
 
 default CONFIG_ROM_STREAM     = 1
 
+##
+## The default compiler
+##
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+
 end