diff options
| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2018-07-31 15:55:54 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-13 12:22:05 +0000 |
| commit | 7130ca0ce0d8ee2db1dd322b4c1bf24615ca0168 (patch) | |
| tree | 2c28880ad6ef9fd78dd15ea5bac63947f93ef8b6 /src | |
| parent | 736b124136aaeecef4ceaeeb056de1ef05504df9 (diff) | |
| download | coreboot-7130ca0ce0d8ee2db1dd322b4c1bf24615ca0168.tar.xz | |
mb/google/poppy/variant/atlas: Update PL2 based on CPU sku
This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27765
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/poppy/variants/atlas/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/variants/atlas/mainboard.c | 45 |
2 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/Makefile.inc b/src/mainboard/google/poppy/variants/atlas/Makefile.inc index ad40bb04d6..06776ffd4a 100644 --- a/src/mainboard/google/poppy/variants/atlas/Makefile.inc +++ b/src/mainboard/google/poppy/variants/atlas/Makefile.inc @@ -19,3 +19,4 @@ romstage-y += memory.c ramstage-y += gpio.c ramstage-y += nhlt.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c new file mode 100644 index 0000000000..07a4e66c1f --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + +#define PL2_AML 18 +#define PL2_KBL 15 + +static uint32_t get_pl2(void) +{ + uint16_t id; + id = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); + /* Assume we only have KLB-Y and AML-Y SKUs */ + if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM) + return PL2_KBL; + + return PL2_AML; +} + +/* Override dev tree settings per board */ +void variant_devtree_update(void) +{ + struct device *root = SA_DEV_ROOT; + config_t *cfg = root->chip_info; + + /* Update PL2 based on CPU */ + cfg->tdp_pl2_override = get_pl2(); +} |