diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-12-09 13:41:32 -0600 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-09 05:41:29 +0200 |
| commit | 7538937d6e7c474dc7c17a1bc3c3591f0e6ef311 (patch) | |
| tree | 65a8e907b52205692500ee9301867a1b01cbe67d /src | |
| parent | f4fe3c303ca5fe8124f48973eef2f798771be0fd (diff) | |
| download | coreboot-7538937d6e7c474dc7c17a1bc3c3591f0e6ef311.tar.xz | |
rambi: export SPI write-protect GPIO correctly
Bay Trail has 3 banks of gpios. Therefore, in order to
properly identify a gpio the specific bank number as well
as the GPIO within that bank is needed. The SPI
write-protect GPIO is GPIO 6 within the SUS bank (offset
0x2000).
BUG=chrome-os-partner:24324
BUG=chrome-os-partner:24408
BRANCH=None
TEST=Built and booted. Looked at GPIO sysfs in the
chromeos_acpi directory.
Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179195
Reviewed-on: http://review.coreboot.org/4995
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rambi/acpi/chromeos.asl | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/src/mainboard/google/rambi/acpi/chromeos.asl b/src/mainboard/google/rambi/acpi/chromeos.asl index 40ffcf0156..e748fb868e 100644 --- a/src/mainboard/google/rambi/acpi/chromeos.asl +++ b/src/mainboard/google/rambi/acpi/chromeos.asl @@ -17,8 +17,20 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * Fields are in the following order. + * - Type: recovery = 1 developer mode = 2 write protect = 3 + * - Active Level - if -1 not a valid gpio + * - GPIO number encoding - if -1 not a valid gpio + * - Chipset Name + * + * Note: On Bay Trail we need to encode gpios within the 3 separate banks + * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded + * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. + */ + Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery - Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer - Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect + // No physical recovery button + Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" }, + Package () { 0x0003, 1, 0x2006, "BayTrail" }, }) |