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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-02-11 11:33:36 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-19 09:28:39 +0000 |
| commit | 7841a7f82416e6ad1d00610cca43a3fa9cc6b320 (patch) | |
| tree | de8b5cfc6fd3b293123f0c413c315dd4d05eabf7 /src | |
| parent | 783982751d26161bb1cb0d923375fabd92940a0f (diff) | |
| download | coreboot-7841a7f82416e6ad1d00610cca43a3fa9cc6b320.tar.xz | |
cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASE
To add a common tsc_freq_mhz() implementation, we need
to guard againts soc-specific duplicate definitions.
Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31341
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/common/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/intel/common/Makefile.inc | 11 | ||||
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_1067x/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_106cx/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/Kconfig | 1 |
7 files changed, 16 insertions, 3 deletions
diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 56bed22a1a..4074d8cc66 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -19,4 +19,7 @@ config SET_IA32_FC_LOCK_BIT However, leaving the lock bit unset will break Windows' detection of VMX support and built-in virtualization features like Hyper-V. +config CPU_INTEL_COMMON_TIMEBASE + bool + endif diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 2fc6da908b..c38e81c380 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,10 @@ ramstage-y += common_init.c -romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c + +ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) +bootblock-y += fsb.c +verstage-y += fsb.c +romstage-y += fsb.c +postcar-y += fsb.c +ramstage-y += fsb.c smm-y += fsb.c +endif diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 15fd804349..11ee9a9ae4 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE select NO_SMM # Microcode header files are delivered in FSP package diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 3ea812573c..c8b9169fe5 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -10,3 +10,4 @@ config CPU_INTEL_MODEL_1067X select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf179e..ba8557c3de 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -13,6 +13,7 @@ config CPU_INTEL_MODEL_106CX select SUPPORT_CPU_UCODE_IN_CBFS select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 10ebcc7044..4ae83f05f9 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -11,3 +11,4 @@ config CPU_INTEL_MODEL_6EX select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 8f053142d4..b86b07e40f 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -11,3 +11,4 @@ config CPU_INTEL_MODEL_6FX select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE |