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authorElyes HAOUAS <ehaouas@noos.fr>2020-06-04 10:15:50 +0200
committerNico Huber <nico.h@gmx.de>2020-06-18 09:10:53 +0000
commit7ac76ecf9127d2b58467a49746b9fc112dd4ef4c (patch)
tree3a0d9e3701fc96305d25115d77ad1d38c87be57f /src
parent6abee842504bc41e1915d19588edeb62d3e0dca7 (diff)
downloadcoreboot-7ac76ecf9127d2b58467a49746b9fc112dd4ef4c.tar.xz
mb/bap/ode_e21XX: Drop left over unmaintained ROMCC board
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Idd907311dde187aa62d29a9d3943b6d5c08a1f71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/bap/Kconfig3
-rw-r--r--src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex217
-rw-r--r--src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex217
-rw-r--r--src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex217
-rw-r--r--src/mainboard/bap/ode_e21XX/BiosCallOuts.c313
-rw-r--r--src/mainboard/bap/ode_e21XX/Kconfig71
-rw-r--r--src/mainboard/bap/ode_e21XX/Kconfig.name3
-rw-r--r--src/mainboard/bap/ode_e21XX/Makefile.inc27
-rw-r--r--src/mainboard/bap/ode_e21XX/OemCustomize.c92
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/gpe.asl57
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/ide.asl2
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/mainboard.asl22
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/routing.asl180
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/si.asl10
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/sleep.asl82
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/superio.asl33
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/thermal.asl2
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl23
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi_tables.c33
-rw-r--r--src/mainboard/bap/ode_e21XX/board_info.txt6
-rw-r--r--src/mainboard/bap/ode_e21XX/cmos.layout55
-rw-r--r--src/mainboard/bap/ode_e21XX/devicetree.cb102
-rw-r--r--src/mainboard/bap/ode_e21XX/dsdt.asl69
-rw-r--r--src/mainboard/bap/ode_e21XX/irq_tables.c88
-rw-r--r--src/mainboard/bap/ode_e21XX/mainboard.c19
-rw-r--r--src/mainboard/bap/ode_e21XX/mptable.c172
-rw-r--r--src/mainboard/bap/ode_e21XX/romstage.c42
27 files changed, 0 insertions, 2157 deletions
diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig
index a262952cf6..44b02e21ca 100644
--- a/src/mainboard/bap/Kconfig
+++ b/src/mainboard/bap/Kconfig
@@ -7,9 +7,6 @@ choice
source "src/mainboard/bap/*/Kconfig.name"
-config BAP_BOARDS_DISABLED
- bool "Boards from vendor are disabled"
-
endchoice
source "src/mainboard/bap/*/Kconfig"
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
deleted file mode 100644
index b6da468a88..0000000000
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
+++ /dev/null
@@ -1,217 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB RAM soldered down on the Q7
-# Memory setting for DDR-1066
-
-# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-# bits[3:0]: 1 = 128 SPD Bytes Used
-# bits[6:4]: 1 = 256 SPD Bytes Total
-# bit7 : 0 = CRC covers bytes 0 ~ 125
-11
-
-# 1 SPD Revision -
-# 0x12 = Revision 1.2
-12
-
-# 2 Key Byte / DRAM Device Type
-# bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-# 3 Key Byte / Module Type
-# bits[3:0]: 3 = SO-DIMM
-# bits[7:4]: reserved
-03
-
-# 4 SDRAM CHIP Density and Banks
-# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
-# bits[6:4]: 0 = 3 (8 banks)
-# bit7 : reserved
-04
-
-# 5 SDRAM Addressing
-# bits[2:0]: 1 = 10 Column Address Bits
-# bits[5:3]: 3 = 15 Row Address Bits
-# bits[7:6]: reserved
-19
-
-# 6 Module Nominal Voltage, VDD
-# bit0 : 0 = 1.5 V operable
-# bit1 : 0 = NOT 1.35 V operable
-# bit2 : 0 = NOT 1.25 V operable
-# bits[7:3]: reserved
-00
-
-# 7 Module Organization
-# bits[2:0]: 2 = 16 bits
-# bits[5:3]: 0 = 1 Rank
-# bits[7:6]: reserved
-02
-
-# 8 Module Memory Bus Width
-# bits[2:0]: 3 = Primary bus width is 64 bits
-# bits[4:3]: 1 = 1 bit (bus width extension ECC)
-# bits[7:5]: reserved
-0B
-
-# 9 Fine Timebase (FTB) Dividend / Divisor
-# bits[3:0]: 0x01 divisor
-# bits[7:4]: 0x01 dividend
-# 1/1 = 1ps
-11
-
-# 10 Medium Timebase (MTB) Dividend
-# 11 Medium Timebase (MTB) Divisor
-# 1 / 8 = .125 ns - used for DDR3
-01 08
-
-# 12 SDRAM Minimum Cycle Time (tCKmin)
-# 0x0F = tCKmin of 1.875 ns = DDR3-1066 (533 MHz clock)
-0F
-
-# 13 Reserved
-00
-
-# 14 CAS Latencies Supported, Least Significant Byte
-# 15 CAS Latencies Supported, Most Significant Byte
-# Cas Latencies of 8 - 5 are supported
-1E 00
-
-# 16 Minimum CAS Latency Time (tAAmin)
-# 0x69 = 13.125ns - DDR3-1066F
-69
-
-# 17 Minimum Write Recovery Time (tWRmin)
-# 0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 0x69 = 13.125ns - DDR3-1066F
-69
-
-# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-# 0x3C = 7.5ns
-3C
-
-# 20 Minimum Row Precharge Delay Time (tRPmin)
-# 0x69 = 13.125ns - DDR3-1066F
-69
-
-# 21 Upper Nibbles for tRAS and tRC
-# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-# 0x12C = 37.5ns - DDR3-1066 (see byte 21)
-2C
-
-# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-# 0x195 = 50.625ns - DDR3-1066F (see byte 21)
-95
-
-# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-# 0x500 = 160ns - for 2 Gigabit chips
-80 07
-
-# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
-3C
-
-# 28 Upper Nibble for tFAWmin
-# 29 Minimum Four Activate Window Delay Time (tFAWmin)
-# 0x0190 = 50ns - DDR3-1066, 2 KB page size
-01 90
-
-# 30 SDRAM Optional Feature
-# bit0 : 1= RZQ/6 supported
-# bit1 : 1 = RZQ/7 supported
-# bits[6:2]: reserved
-# bit7 : 0 = DLL Off mode supported
-03
-
-# 31 SDRAM Thermal and Refresh Options
-# bit0 : 0 = Temp up to 95c supported
-# bit1 : 0 = 85-95c uses 2x refresh rate
-# bit2 : 1 = Auto Self Refresh supported
-# bit3 : 0 = no on die thermal sensor
-# bits[6:4]: reserved
-# bit7 : 0 = partial self refresh supported
-04
-
-# 32 Module Thermal Sensor
-# 0 = Thermal sensor not incorporated onto this assembly
-00
-
-# 33 SDRAM Device Type
-# bits[1:0]: 0 = Signal Loading not specified
-# bits[3:2]: reserved
-# bits[6:4]: 0 = Die count not specified
-# bit7 : 0 = Standard Monolithic DRAM Device
-00
-
-# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00 00 00 00 00
-
-# 39 - 59 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-# 60 Raw Card Extension, Module Nominal Height
-# bits[4:0]: 0 = <= 15mm tall
-# bits[7:5]: 0 = raw card revision 0-3
-00
-
-# 61 Module Maximum Thickness
-# bits[3:0]: 0 = thickness front <= 1mm
-# bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-# 62 Reference Raw Card Used
-# bits[4:0]: 0 = Reference Raw card A used
-# bits[6:5]: 0 = revision 0
-# bit7 : 0 = Reference raw cards A through AL
-00
-
-# 63 Address Mapping from Edge Connector to DRAM
-# bit0 : 0 = standard mapping (not mirrored)
-# bits[7:1]: reserved
-00
-
-# 64 - 116 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-# 0x80AD = Hynix
-80 AD
-
-# 119 Module ID: Module Manufacturing Location - oem specified
-# 120 Module ID: Module Manufacture Year in BCD
-# 0x00 = 2000
-00 00
-
-# 121 Module ID: Module Manufacture week
-# 0x00 = 0th week
-00
-
-# 122 - 125: Module Serial Number
-00 00 00 00
-
-# 126 - 127: Cyclical Redundancy Code
-E9 40
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
deleted file mode 100644
index bfd15cc55c..0000000000
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
+++ /dev/null
@@ -1,217 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB RAM soldered down on the Q7
-# Memory setting for DDR-1333
-
-# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-# bits[3:0]: 1 = 128 SPD Bytes Used
-# bits[6:4]: 1 = 256 SPD Bytes Total
-# bit7 : 0 = CRC covers bytes 0 ~ 125
-11
-
-# 1 SPD Revision -
-# 0x13 = Revision 1.3
-13
-
-# 2 Key Byte / DRAM Device Type
-# bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-# 3 Key Byte / Module Type
-# bits[3:0]: 3 = SO-DIMM
-# bits[7:4]: reserved
-03
-
-# 4 SDRAM CHIP Density and Banks
-# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
-# bits[6:4]: 0 = 3 (8 banks)
-# bit7 : reserved
-04
-
-# 5 SDRAM Addressing
-# bits[2:0]: 1 = 10 Column Address Bits
-# bits[5:3]: 3 = 15 Row Address Bits
-# bits[7:6]: reserved
-19
-
-# 6 Module Nominal Voltage, VDD
-# bit0 : 0 = 1.5 V operable
-# bit1 : 0 = NOT 1.35 V operable
-# bit2 : 0 = NOT 1.25 V operable
-# bits[7:3]: reserved
-00
-
-# 7 Module Organization
-# bits[2:0]: 2 = 16 bits
-# bits[5:3]: 0 = 1 Rank
-# bits[7:6]: reserved
-02
-
-# 8 Module Memory Bus Width
-# bits[2:0]: 3 = Primary bus width is 64 bits
-# bits[4:3]: 1 = 1 bit (bus width extension ECC)
-# bits[7:5]: reserved
-0B
-
-# 9 Fine Timebase (FTB) Dividend / Divisor
-# bits[3:0]: 0x01 divisor
-# bits[7:4]: 0x01 dividend
-# 1/1 = 1ps
-11
-
-# 10 Medium Timebase (MTB) Dividend
-# 11 Medium Timebase (MTB) Divisor
-# 1 / 8 = .125 ns - used for DDR3
-01 08
-
-# 12 SDRAM Minimum Cycle Time (tCKmin)
-# 0x0C = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
-0C
-
-# 13 Reserved
-00
-
-# 14 CAS Latencies Supported, Least Significant Byte
-# 15 CAS Latencies Supported, Most Significant Byte
-# Cas Latencies of 9 - 5 are supported (no 7)
-36 00
-
-# 16 Minimum CAS Latency Time (tAAmin)
-# 0x6C = 13.5ns - DDR3-1333H
-6C
-
-# 17 Minimum Write Recovery Time (tWRmin)
-# 0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 0x6C = 13.5ns - DDR3-1333H
-6C
-
-# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-# 0x3C = 7.5ns
-3C
-
-# 20 Minimum Row Precharge Delay Time (tRPmin)
-# 0x6C = 13.5ns - DDR3-1333H
-6C
-
-# 21 Upper Nibbles for tRAS and tRC
-# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-# 0x120 = 36ns - DDR3-1333 (see byte 21)
-20
-
-# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-# 0x18C = 49.5ns - DDR3-1333H (see byte 21)
-8C
-
-# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-# 0x500 = 160ns - for 2 Gigabit chips
-80 07
-
-# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
-3C
-
-# 28 Upper Nibble for tFAWmin
-# 29 Minimum Four Activate Window Delay Time (tFAWmin)
-# 0x0168 = 45ns - DDR3-1333, 2 KB page size
-01 68
-
-# 30 SDRAM Optional Feature
-# bit0 : 1= RZQ/6 supported
-# bit1 : 1 = RZQ/7 supported
-# bits[6:2]: reserved
-# bit7 : 0 = DLL Off mode supported
-03
-
-# 31 SDRAM Thermal and Refresh Options
-# bit0 : 0 = Temp up to 95c supported
-# bit1 : 0 = 85-95c uses 2x refresh rate
-# bit2 : 1 = Auto Self Refresh supported
-# bit3 : 0 = no on die thermal sensor
-# bits[6:4]: reserved
-# bit7 : 0 = partial self refresh supported
-04
-
-# 32 Module Thermal Sensor
-# 0 = Thermal sensor not incorporated onto this assembly
-00
-
-# 33 SDRAM Device Type
-# bits[1:0]: 0 = Signal Loading not specified
-# bits[3:2]: reserved
-# bits[6:4]: 0 = Die count not specified
-# bit7 : 0 = Standard Monolithic DRAM Device
-00
-
-# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00 00 00 00 00
-
-# 39 - 59 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-# 60 Raw Card Extension, Module Nominal Height
-# bits[4:0]: 0 = <= 15mm tall
-# bits[7:5]: 0 = raw card revision 0-3
-00
-
-# 61 Module Maximum Thickness
-# bits[3:0]: 0 = thickness front <= 1mm
-# bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-# 62 Reference Raw Card Used
-# bits[4:0]: 0 = Reference Raw card A used
-# bits[6:5]: 0 = revision 0
-# bit7 : 0 = Reference raw cards A through AL
-00
-
-# 63 Address Mapping from Edge Connector to DRAM
-# bit0 : 0 = standard mapping (not mirrored)
-# bits[7:1]: reserved
-00
-
-# 64 - 116 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-# 0x80AD = Hynix
-80 AD
-
-# 119 Module ID: Module Manufacturing Location - oem specified
-# 120 Module ID: Module Manufacture Year in BCD
-# 0x00 = 2000
-00 00
-
-# 121 Module ID: Module Manufacture week
-# 0x00 = 0th week
-00
-
-# 122 - 125: Module Serial Number
-00 00 00 00
-
-# 126 - 127: Cyclical Redundancy Code
-95 b9
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
deleted file mode 100644
index 8b61fcbd78..0000000000
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
+++ /dev/null
@@ -1,217 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB RAM soldered down on the Q7
-# Memory setting for DDR-800
-
-# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-# bits[3:0]: 1 = 128 SPD Bytes Used
-# bits[6:4]: 1 = 256 SPD Bytes Total
-# bit7 : 0 = CRC covers bytes 0 ~ 125
-11
-
-# 1 SPD Revision -
-# 0x11 = Revision 1.1
-11
-
-# 2 Key Byte / DRAM Device Type
-# bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-# 3 Key Byte / Module Type
-# bits[3:0]: 3 = SO-DIMM
-# bits[7:4]: reserved
-03
-
-# 4 SDRAM CHIP Density and Banks
-# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
-# bits[6:4]: 0 = 3 (8 banks)
-# bit7 : reserved
-04
-
-# 5 SDRAM Addressing
-# bits[2:0]: 1 = 10 Column Address Bits
-# bits[5:3]: 3 = 15 Row Address Bits
-# bits[7:6]: reserved
-19
-
-# 6 Module Nominal Voltage, VDD
-# bit0 : 0 = 1.5 V operable
-# bit1 : 0 = NOT 1.35 V operable
-# bit2 : 0 = NOT 1.25 V operable
-# bits[7:3]: reserved
-00
-
-# 7 Module Organization
-# bits[2:0]: 2 = 16 bits
-# bits[5:3]: 0 = 1 Rank
-# bits[7:6]: reserved
-02
-
-# 8 Module Memory Bus Width
-# bits[2:0]: 3 = Primary bus width is 64 bits
-# bits[4:3]: 1 = 1 bit (bus width extension ECC)
-# bits[7:5]: reserved
-0B
-
-# 9 Fine Timebase (FTB) Dividend / Divisor
-# bits[3:0]: 0x01 divisor
-# bits[7:4]: 0x01 dividend
-# 1/1 = 1ps
-11
-
-# 10 Medium Timebase (MTB) Dividend
-# 11 Medium Timebase (MTB) Divisor
-# 1 / 8 = .125 ns - used for DDR3
-01 08
-
-# 12 SDRAM Minimum Cycle Time (tCKmin)
-# 0x14 = tCKmin of 2.5 ns = DDR3-800 (400 MHz clock)
-14
-
-# 13 Reserved
-00
-
-# 14 CAS Latencies Supported, Least Significant Byte
-# 15 CAS Latencies Supported, Most Significant Byte
-# CAS Latencies of 6 - 5 are supported
-06 00
-
-# 16 Minimum CAS Latency Time (tAAmin)
-# 0x78 = 15ns - DDR3-800E
-78
-
-# 17 Minimum Write Recovery Time (tWRmin)
-# 0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 0x6E = 15ns - DDR3-800E
-78
-
-# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-# 0x3C = 7.5ns
-3C
-
-# 20 Minimum Row Precharge Delay Time (tRPmin)
-# 0x6E = 15ns - DDR3-800E
-78
-
-# 21 Upper Nibbles for tRAS and tRC
-# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-# 0x12C = 37.5ns - DDR3-800E (see byte 21)
-2C
-
-# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-# 0x1A4 = 52.5ns - DDR3-800E (see byte 21)
-A4
-
-# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-# 0x780 = 208ns - for 4 Gigabit chips
-80 07
-
-# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
-3C
-
-# 28 Upper Nibble for tFAWmin
-# 29 Minimum Four Activate Window Delay Time (tFAWmin)
-# 0x0190 = 50ns - DDR3-800, 2 KB page size
-01 90
-
-# 30 SDRAM Optional Feature
-# bit0 : 1= RZQ/6 supported
-# bit1 : 1 = RZQ/7 supported
-# bits[6:2]: reserved
-# bit7 : 0 = DLL Off mode supported
-03
-
-# 31 SDRAM Thermal and Refresh Options
-# bit0 : 0 = Temp up to 95c supported
-# bit1 : 0 = 85-95c uses 2x refresh rate
-# bit2 : 1 = Auto Self Refresh supported
-# bit3 : 0 = no on die thermal sensor
-# bits[6:4]: reserved
-# bit7 : 0 = partial self refresh supported
-04
-
-# 32 Module Thermal Sensor
-# 0 = Thermal sensor not incorporated onto this assembly
-00
-
-# 33 SDRAM Device Type
-# bits[1:0]: 0 = Signal Loading not specified
-# bits[3:2]: reserved
-# bits[6:4]: 0 = Die count not specified
-# bit7 : 0 = Standard Monolithic DRAM Device
-00
-
-# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00 00 00 00 00
-
-# 39 - 59 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-# 60 Raw Card Extension, Module Nominal Height
-# bits[4:0]: 0 = <= 15mm tall
-# bits[7:5]: 0 = raw card revision 0-3
-00
-
-# 61 Module Maximum Thickness
-# bits[3:0]: 0 = thickness front <= 1mm
-# bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-# 62 Reference Raw Card Used
-# bits[4:0]: 0 = Reference Raw card A used
-# bits[6:5]: 0 = revision 0
-# bit7 : 0 = Reference raw cards A through AL
-00
-
-# 63 Address Mapping from Edge Connector to DRAM
-# bit0 : 0 = standard mapping (not mirrored)
-# bits[7:1]: reserved
-00
-
-# 64 - 116 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-# 0x80AD = Hynix
-80 AD
-
-# 119 Module ID: Module Manufacturing Location - oem specified
-# 120 Module ID: Module Manufacture Year in BCD
-# 0x00 = 2000
-00 00
-
-# 121 Module ID: Module Manufacture week
-# 0x00 = 0th week
-00
-
-# 122 - 125: Module Serial Number
-00 00 00 00
-
-# 126 - 127: Cyclical Redundancy Code
-48 91
diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
deleted file mode 100644
index faf3b95f39..0000000000
--- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <FchPlatform.h>
-#include <spd_bin.h>
-
-#include "imc.h"
-#include "hudson.h"
-
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
-static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
- {AGESA_READ_SPD, board_ReadSpd_from_cbfs },
- {AGESA_DO_RESET, agesa_Reset },
- {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
- {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
- {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
- {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
- {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
- {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
- {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/**
- * Realtek ALC272 CODEC Verb Table
- */
-static const CODEC_ENTRY Alc272_VerbTbl[] = {
- {0x11, 0x411111F0}, // - SPDIF_OUT2
- {0x12, 0x411111F0}, // - DMIC_1/2
- {0x13, 0x411111F0}, // - DMIC_3/4
- {0x14, 0x411111F0}, // Port D - LOUT1
- {0x15, 0x411111F0}, // Port A - LOUT2
- {0x16, 0x411111F0}, //
- {0x17, 0x411111F0}, // Port H - MONO
- {0x18, 0x01a19840}, // Port B - MIC1
- {0x19, 0x411111F0}, // Port F - MIC2
- {0x1a, 0x01813030}, // Port C - LINE1
- {0x1b, 0x411111F0}, // Port E - LINE2
- {0x1d, 0x40251E05}, // - PCBEEP
- {0x1e, 0x01441120}, // - SPDIF_OUT1
- {0x21, 0x01214010}, // Port I - HPOUT
- {0xff, 0xffffffff}
-};
-
-static const CODEC_TBL_LIST CodecTableList[] =
-{
- {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]},
- {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
-};
-
-#define FAN_INPUT_INTERNAL_DIODE 0
-#define FAN_INPUT_TEMP0 1
-#define FAN_INPUT_TEMP1 2
-#define FAN_INPUT_TEMP2 3
-#define FAN_INPUT_TEMP3 4
-#define FAN_INPUT_TEMP0_FILTER 5
-#define FAN_INPUT_ZERO 6
-#define FAN_INPUT_DISABLED 7
-
-#define FAN_AUTOMODE (1 << 0)
-#define FAN_LINEARMODE (1 << 1)
-#define FAN_STEPMODE ~(1 << 1)
-#define FAN_POLARITY_HIGH (1 << 2)
-#define FAN_POLARITY_LOW ~(1 << 2)
-
-/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
-#define FREQ_28KHZ 0x0
-#define FREQ_25KHZ 0x1
-#define FREQ_23KHZ 0x2
-#define FREQ_21KHZ 0x3
-#define FREQ_29KHZ 0x4
-#define FREQ_18KHZ 0x5
-#define FREQ_100HZ 0xF7
-#define FREQ_87HZ 0xF8
-#define FREQ_58HZ 0xF9
-#define FREQ_44HZ 0xFA
-#define FREQ_35HZ 0xFB
-#define FREQ_29HZ 0xFC
-#define FREQ_22HZ 0xFD
-#define FREQ_14HZ 0xFE
-#define FREQ_11HZ 0xFF
-
-/*
- * Hardware Monitor Fan Control
- * Hardware limitation:
- * HWM will fail to read the input temperature via I2C if other
- * software switches the I2C address. AMD recommends using IMC
- * to control fans, instead of HWM.
- */
-static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
-{
- FCH_HWM_FAN_CTR oem_factl[5] = {
- /*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */
- /* DB-FT3 FanOUT0 Fan header J32 */
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- /* DB-FT3 FanOUT1 Fan header J31*/
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
- };
- LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
-
- /* Enable IMC fan control. the recommended way */
- if (CONFIG(HUDSON_IMC_FWM)) {
- /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
- FchParams->Hwm.HwMonitorEnable = TRUE;
- FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */
-
- FchParams->Imc.ImcEnable = TRUE;
- FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
- FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
-
- LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
-
- /* Thermal Zone Parameter */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e; //6 | BIT3;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
-
- /* IMC Fan Policy temperature thresholds */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
-
- /* IMC Fan Policy PWM Settings */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
-
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0;
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM stepping rate in unit of PWM level percentage */
- FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
-
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
- FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
-
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */
- FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */
-
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2;
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM stepping rate in unit of PWM level percentage */
- FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0;
-
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0;
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM stepping rate in unit of PWM level percentage */
- FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
-
- /* IMC Function */
- FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8;
-
- /* NOTE:
- * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
- * AGESA put EcDefaultMessage as global data in ROM, so we can't override it.
- * so we remove it from AGESA code. Please See FchInitLateHwm.
- */
- } else {
- /* HWM fan control, using the alternative method */
- FchParams->Imc.ImcEnable = FALSE;
- FchParams->Hwm.HwMonitorEnable = TRUE;
- FchParams->Hwm.HwmFchtsiAutoPoll = TRUE; /* 1 enable, 0 disable TSI Auto Polling */
- }
-}
-
-/**
- * Fch Oem setting callback
- *
- * Configure platform specific Hudson device,
- * such Azalia, SATA, IMC etc.
- */
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
-{
- AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
- if (StdHeader->Func == AMD_INIT_RESET) {
- FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
- FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
- FchParams->FchReset.SataEnable = hudson_sata_enable();
- FchParams->FchReset.IdeEnable = hudson_ide_enable();
- FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
- FchParams->FchReset.Xhci1Enable = FALSE;
- } else if (StdHeader->Func == AMD_INIT_ENV) {
- FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
- /* Azalia Controller OEM Codec Table Pointer */
- FchParams->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
- /* Azalia Controller Front Panel OEM Table Pointer */
-
- /* Fan Control */
- oem_fan_control(FchParams);
-
- /* XHCI configuration */
- FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
- FchParams->Usb.Xhci1Enable = FALSE;
-
- /* sata configuration */
- FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
- switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
- case SataRaid:
- case SataAhci:
- case SataAhci7804:
- case SataLegacyIde:
- FchParams->Sata.SataIdeMode = FALSE;
- break;
- case SataIde2Ahci:
- case SataIde2Ahci7804:
- default: /* SataNativeIde */
- FchParams->Sata.SataIdeMode = TRUE;
- break;
- }
- }
- printk(BIOS_DEBUG, "Done\n");
-
- return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
- AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- u8 index;
-
- if (!ENV_ROMSTAGE)
- return AGESA_UNSUPPORTED;
-
- if (CONFIG(BAP_E21_DDR3_1066))
- index = 1;
- else if (CONFIG(BAP_E21_DDR3_1333))
- index = 2;
- else /* CONFIG_BAP_E21_DDR3_800 */
- index = 0;
-
- if (info->MemChannelId > 0)
- return AGESA_UNSUPPORTED;
- if (info->SocketId != 0)
- return AGESA_UNSUPPORTED;
- if (info->DimmId != 0)
- return AGESA_UNSUPPORTED;
-
- /* Read index 0, first SPD_SIZE bytes of spd.bin file. */
- if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0)
- die("No SPD data\n");
-
- return AGESA_SUCCESS;
-}
diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig
deleted file mode 100644
index 4d77280060..0000000000
--- a/src/mainboard/bap/ode_e21XX/Kconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config BOARD_ODE_E21XX
- def_bool n
-
-if BOARD_ODE_E21XX
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select CPU_AMD_PI_00730F01
- select NORTHBRIDGE_AMD_PI_00730F01
- select SOUTHBRIDGE_AMD_PI_AVALON
- select DEFAULT_POST_ON_LPC
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_8192
- select GFXUMA
- select SUPERIO_FINTEK_F81866D
-
-config MAINBOARD_DIR
- string
- default "bap/ode_e21XX"
-
-config MAINBOARD_PART_NUMBER
- string
- default "ODE_E21XX"
-
-config MAX_CPUS
- int
- default 4
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-config ONBOARD_VGA_IS_PRIMARY
- bool
- default y
-
-config HUDSON_LEGACY_FREE
- bool
- default y
-
-choice
- prompt "Select DDR3 clock"
- default BAP_E21_DDR3_1333
- help
- Select your preferenced DDR3 clock setting.
-
- Note: This option changes the total power consumption.
-
- If unsure, use DDR3-1333.
-
-config BAP_E21_DDR3_800
- bool "Select DDR3-800"
-
-config BAP_E21_DDR3_1066
- bool "Select DDR3-1066"
-
-config BAP_E21_DDR3_1333
- bool "Select DDR3-1333"
-
-endchoice
-
-config DIMM_SPD_SIZE
- int
- default 128
-
-endif # BOARD_ODE_E21XX
diff --git a/src/mainboard/bap/ode_e21XX/Kconfig.name b/src/mainboard/bap/ode_e21XX/Kconfig.name
deleted file mode 100644
index 64665daea7..0000000000
--- a/src/mainboard/bap/ode_e21XX/Kconfig.name
+++ /dev/null
@@ -1,3 +0,0 @@
-# Disabled
-#config BOARD_ODE_E21XX
-# bool "ODE_e21xx"
diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc
deleted file mode 100644
index 2abdc71607..0000000000
--- a/src/mainboard/bap/ode_e21XX/Makefile.inc
+++ /dev/null
@@ -1,27 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-
-## DIMM SPD for on-board memory
-SPD_BIN = $(obj)/spd.bin
-
-# Order of names in SPD_SOURCES is important!
-SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066 BAP_Q7_1333
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do for c in $$(cat $$f | grep -v ^#); \
- do printf $$(printf '\%o' 0x$$c); \
- done; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c
deleted file mode 100644
index cc3818925c..0000000000
--- a/src/mainboard/bap/ode_e21XX/OemCustomize.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
- /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 3),
- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmDisabled, 0x02, 0)
- },
- /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmDisabled, 0x03, 0)
- },
- /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmDisabled, 0x04, 0)
- },
- /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
- {
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmDisabled, 0x05, 0)
- }
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
- /* eDP0 to LVDS connector */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
- },
- /* DP1 to HDMI */
- {
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
- },
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
- .Flags = DESCRIPTOR_TERMINATE_LIST,
- .SocketId = 0,
- .PciePortList = PortList,
- .DdiLinkList = DdiList
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * OemCustomizeInitEarly
- *
- * Description:
- * This stub function will call the host environment through the binary block
- * interface (call-out port) to provide a user hook opportunity
- *
- * Parameters:
- * @param[in] *InitEarly
- *
- * @retval VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID
-OemCustomizeInitEarly (
- IN OUT AMD_EARLY_PARAMS *InitEarly
- )
-{
- InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-}
diff --git a/src/mainboard/bap/ode_e21XX/acpi/gpe.asl b/src/mainboard/bap/ode_e21XX/acpi/gpe.asl
deleted file mode 100644
index cdf1f058e9..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi/gpe.asl
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) { /* Start Scope GPE */
-
- /* General event 3 */
- Method(_L03) {
- /* DBGO("\\_GPE\\_L00\n") */
- }
-
- /* Legacy PM event */
- Method(_L08) {
- /* DBGO("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method(_L09) {
- /* DBGO("\\_GPE\\_L09\n") */
- /* Notify (\_TZ.TZ00, 0x80) */
- }
-
- /* USB controller PME# */
- Method(_L0B) {
- /* DBGO("\\_GPE\\_L0B\n") */
- Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* ExtEvent0 SCI event */
- Method(_L10) {
- /* DBGO("\\_GPE\\_L10\n") */
- }
-
- /* ExtEvent1 SCI event */
- Method(_L11) {
- /* DBGO("\\_GPE\\_L11\n") */
- }
-
- /* GPIO0 or GEvent8 event */
- Method(_L18) {
- /* DBGO("\\_GPE\\_L18\n") */
- Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Azalia SCI event */
- Method(_L1B) {
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-} /* End Scope GPE */
diff --git a/src/mainboard/bap/ode_e21XX/acpi/ide.asl b/src/mainboard/bap/ode_e21XX/acpi/ide.asl
deleted file mode 100644
index 4a3eac89a3..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi/ide.asl
+++ /dev/null
@@ -1,2 +0,0 @@
-/* No license required */
-/* No IDE functionality */
diff --git a/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl b/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl
deleted file mode 100644
index 63c7356120..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi/mainboard.asl
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Memory related values */
-Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
-Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-Name(PBLN, 0x0) /* Length of BIOS area */
-
-Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
-Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
-Name(HPBA, 0xFED00000) /* Base address of HPET table */
-
-/* Some global data */
-Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-Name(OSV, Ones) /* Assume nothing */
-Name(PMOD, One) /* Assume APIC */
-
-/* AcpiGpe0Blk */
-OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
- Field(GP0B, ByteAcc, NoLock, Preserve) {
- , 11,
- USBS, 1,
-}
diff --git a/src/mainboard/bap/ode_e21XX/acpi/routing.asl b/src/mainboard/bap/ode_e21XX/acpi/routing.asl
deleted file mode 100644
index d08e162e4d..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi/routing.asl
+++ /dev/null
@@ -1,180 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-#include <acpi/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
- )
- {
- #include "routing.asl"
- }
-*/
-
-/* Routing is in System Bus scope */
-Name(PR0, Package(){
- /* NB devices */
- /* Bus 0, Dev 0 - F16 Host Controller */
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
- /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
- Package(){0x0001FFFF, 0, INTB, 0 },
- Package(){0x0001FFFF, 1, INTC, 0 },
-
-
- /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
- Package(){0x0002FFFF, 0, INTC, 0 },
- Package(){0x0002FFFF, 1, INTD, 0 },
- Package(){0x0002FFFF, 2, INTA, 0 },
- Package(){0x0002FFFF, 3, INTB, 0 },
-
- /* FCH devices */
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
- Package(){0x0014FFFF, 0, INTA, 0 },
- Package(){0x0014FFFF, 1, INTB, 0 },
- Package(){0x0014FFFF, 2, INTC, 0 },
- Package(){0x0014FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
- /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
- Package(){0x0012FFFF, 0, INTC, 0 },
- Package(){0x0012FFFF, 1, INTB, 0 },
-
- Package(){0x0013FFFF, 0, INTC, 0 },
- Package(){0x0013FFFF, 1, INTB, 0 },
-
- Package(){0x0016FFFF, 0, INTC, 0 },
- Package(){0x0016FFFF, 1, INTB, 0 },
-
- /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
- Package(){0x0010FFFF, 0, INTC, 0 },
- Package(){0x0010FFFF, 1, INTB, 0 },
-
- /* Bus 0, Dev 17 - SATA controller */
- Package(){0x0011FFFF, 0, INTD, 0 },
-
-})
-
-Name(APR0, Package(){
- /* NB devices in APIC mode */
- /* Bus 0, Dev 0 - F15 Host Controller */
-
- /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
- Package(){0x0001FFFF, 0, 0, 44 },
- Package(){0x0001FFFF, 1, 0, 45 },
-
- /* Bus 0, Dev 2 - PCIe Bridges */
- Package(){0x0002FFFF, 0, 0, 24 },
- Package(){0x0002FFFF, 1, 0, 25 },
- Package(){0x0002FFFF, 2, 0, 26 },
- Package(){0x0002FFFF, 3, 0, 27 },
-
-
- /* SB devices in APIC mode */
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
- Package(){0x0014FFFF, 0, 0, 16 },
- Package(){0x0014FFFF, 1, 0, 17 },
- Package(){0x0014FFFF, 2, 0, 18 },
- Package(){0x0014FFFF, 3, 0, 19 },
-
- /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
- /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
- Package(){0x0012FFFF, 0, 0, 18 },
- Package(){0x0012FFFF, 1, 0, 17 },
-
- Package(){0x0013FFFF, 0, 0, 18 },
- Package(){0x0013FFFF, 1, 0, 17 },
-
- Package(){0x0016FFFF, 0, 0, 18 },
- Package(){0x0016FFFF, 1, 0, 17 },
-
- /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
- Package(){0x0010FFFF, 0, 0, 0x12},
- Package(){0x0010FFFF, 1, 0, 0x11},
-
- /* Bus 0, Dev 17 - SATA controller */
- Package(){0x0011FFFF, 0, 0, 19 },
-
-})
-
-Name(PS2, Package(){
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS2, Package(){
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
-})
-
-/* GFX */
-Name(PS4, Package(){
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
- Package(){0x0000FFFF, 0, 0, 24 },
- Package(){0x0000FFFF, 1, 0, 25 },
- Package(){0x0000FFFF, 2, 0, 26 },
- Package(){0x0000FFFF, 3, 0, 27 },
-})
-
-/* GPP 0 */
-Name(PS5, Package(){
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
-})
-Name(APS5, Package(){
- Package(){0x0000FFFF, 0, 0, 28 },
- Package(){0x0000FFFF, 1, 0, 29 },
- Package(){0x0000FFFF, 2, 0, 30 },
- Package(){0x0000FFFF, 3, 0, 31 },
-})
-
-/* GPP 1 */
-Name(PS6, Package(){
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS6, Package(){
- Package(){0x0000FFFF, 0, 0, 32 },
- Package(){0x0000FFFF, 1, 0, 33 },
- Package(){0x0000FFFF, 2, 0, 34 },
- Package(){0x0000FFFF, 3, 0, 35 },
-})
-
-/* GPP 2 */
-Name(PS7, Package(){
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
-})
-Name(APS7, Package(){
- Package(){0x0000FFFF, 0, 0, 36 },
- Package(){0x0000FFFF, 1, 0, 37 },
- Package(){0x0000FFFF, 2, 0, 38 },
- Package(){0x0000FFFF, 3, 0, 39 },
-})
-
-/* GPP 3 */
-Name(PS8, Package(){
- Package(){0x0000FFFF, 0, INTA, 0 },
- Package(){0x0000FFFF, 1, INTB, 0 },
- Package(){0x0000FFFF, 2, INTC, 0 },
- Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS8, Package(){
- Package(){0x0000FFFF, 0, 0, 40 },
- Package(){0x0000FFFF, 1, 0, 41 },
- Package(){0x0000FFFF, 2, 0, 42 },
- Package(){0x0000FFFF, 3, 0, 43 },
-})
diff --git a/src/mainboard/bap/ode_e21XX/acpi/si.asl b/src/mainboard/bap/ode_e21XX/acpi/si.asl
deleted file mode 100644
index 25c1dca190..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi/si.asl
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_SI) {
- Method(_SST, 1) {
- /* DBGO("\\_SI\\_SST\n") */
- /* DBGO(" New Indicator state: ") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
- }
-} /* End Scope SI */
diff --git a/src/mainboard/bap/ode_e21XX/acpi/sleep.asl b/src/mainboard/bap/ode_e21XX/acpi/sleep.asl
deleted file mode 100644
index dbe9bd1a69..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi/sleep.asl
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-* Entry:
-* Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-* -none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method. This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver. This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-
-External(\_SB.APTS, MethodObj)
-External(\_SB.AWAK, MethodObj)
-
-Method(_PTS, 1) {
- /* DBGO("\\_PTS\n") */
- /* DBGO("From S0 to S") */
- /* DBGO(Arg0) */
- /* DBGO("\n") */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- Store(7, UPWS)
- \_SB.APTS(Arg0)
-} /* End Method(\_PTS) */
-
-/*
-* \_BFS OEM Back From Sleep method
-*
-* Entry:
-* Arg0=The value of the sleeping state S1=1, S2=2
-*
-* Exit:
-* -none-
-*/
-Method(\_BFS, 1) {
- /* DBGO("\\_BFS\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-}
-
-/*
-* \_WAK System Wake method
-*
-* Entry:
-* Arg0=The value of the sleeping state S1=1, S2=2
-*
-* Exit:
-* Return package of 2 DWords
-* Dword 1 - Status
-* 0x00000000 wake succeeded
-* 0x00000001 Wake was signaled but failed due to lack of power
-* 0x00000002 Wake was signaled but failed due to thermal condition
-* Dword 2 - Power Supply state
-* if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
- /* DBGO("\\_WAK\n") */
- /* DBGO("From S") */
- /* DBGO(Arg0) */
- /* DBGO(" to S0\n") */
-
- /* clear USB wake up signal */
- Store(1, USBS)
-
- \_SB.AWAK(Arg0)
-
- Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/bap/ode_e21XX/acpi/superio.asl b/src/mainboard/bap/ode_e21XX/acpi/superio.asl
deleted file mode 100644
index e12fd7b217..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi/superio.asl
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* SuperIO support for Windows */
-
-Device (UAR1) {
- Name (_HID, EISAID ("PNP0501"))
- Name (_UID, 1)
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
- IRQNoFlags () {4}
- })
- Name (_PRS, ResourceTemplate ()
- {
- IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
- IRQNoFlags () {4}
- })
-}
-
-Device (UAR2) {
- Name (_HID, EISAID ("PNP0501"))
- Name (_UID, 2)
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
- IRQNoFlags () {3}
- })
- Name (_PRS, ResourceTemplate ()
- {
- IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
- IRQNoFlags () {3}
- })
-}
diff --git a/src/mainboard/bap/ode_e21XX/acpi/thermal.asl b/src/mainboard/bap/ode_e21XX/acpi/thermal.asl
deleted file mode 100644
index 73077ac4d3..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi/thermal.asl
+++ /dev/null
@@ -1,2 +0,0 @@
-/* No license required */
-/* No thermal zone functionality */
diff --git a/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl
deleted file mode 100644
index 52b2daa407..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-/*
-#include <acpi/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
- )
- {
- #include "usb.asl"
- }
-*/
-
-/* USB overcurrent mapping pins. */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
diff --git a/src/mainboard/bap/ode_e21XX/acpi_tables.c b/src/mainboard/bap/ode_e21XX/acpi_tables.c
deleted file mode 100644
index 2cc9bf58e1..0000000000
--- a/src/mainboard/bap/ode_e21XX/acpi_tables.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <arch/ioapic.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB800 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
- IO_APIC_ADDR, 0);
-
- /* TODO: Remove the hardcode */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
- 0xFEC20000, 24);
-
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edge-triggered, Active high */
-
- /* create all subtables for processors */
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
- /* 1: LINT1 connect to NMI */
-
- return current;
-}
diff --git a/src/mainboard/bap/ode_e21XX/board_info.txt b/src/mainboard/bap/ode_e21XX/board_info.txt
deleted file mode 100644
index dffb350694..0000000000
--- a/src/mainboard/bap/ode_e21XX/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: ODE_e21xx
-Board URL: http://www.unibap.com/advanced-heterogeneous-computing-modules/
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/bap/ode_e21XX/cmos.layout b/src/mainboard/bap/ode_e21XX/cmos.layout
deleted file mode 100644
index ade4c04bf3..0000000000
--- a/src/mainboard/bap/ode_e21XX/cmos.layout
+++ /dev/null
@@ -1,55 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 400Mhz
-8 1 333Mhz
-8 2 266Mhz
-8 3 200Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/bap/ode_e21XX/devicetree.cb b/src/mainboard/bap/ode_e21XX/devicetree.cb
deleted file mode 100644
index 56acc20a82..0000000000
--- a/src/mainboard/bap/ode_e21XX/devicetree.cb
+++ /dev/null
@@ -1,102 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/pi/00730F01/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/pi/00730F01
- device lapic 0 on end
- end
- end
-
- device domain 0 on
- subsystemid 0x1022 0x1410 inherit
-
- chip northbridge/amd/pi/00730F01
- device pci 0.0 on end # Root Complex
- device pci 0.2 off end # IOMMU
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
- device pci 1.1 on end # Internal Multimedia
- device pci 2.0 on end # PCIe Host Bridge
- device pci 2.1 on end # x4 PCIe slot
- device pci 2.2 on end # PCIe Q7 Realtek GBit LAN
- device pci 2.3 on end # PCIe CB Realtek GBit LAN
- device pci 2.4 on end # PCIe x2 BAP FPGA
- device pci 8.0 on end # Platform Security Processor
- end #chip northbridge/amd/pi/00730F01
-
- chip southbridge/amd/pi/hudson
- device pci 10.0 on end # XHCI HC0
- device pci 11.0 on end # SATA
- device pci 12.0 on end # EHCI #0
- device pci 13.0 on end # EHCI #1
- device pci 14.0 on end # SMBus
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x439d
- chip superio/fintek/f81866d
- register "hwm_amd_tsi_addr" = "0x98" # Set to AMD
- register "hwm_amd_tsi_control" = "0x02" # Set to AMD
- register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM
- register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode
- register "hwm_fan3_control" = "0x00" # Fan control 23kHz
- register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz
- register "hwm_fan2_bound1" = "0x3C" # 60°C
- register "hwm_fan2_bound2" = "0x32" # 50°C
- register "hwm_fan2_bound3" = "0x28" # 40°C
- register "hwm_fan2_bound4" = "0x1E" # 30°C
- register "hwm_fan2_seg1_speed" = "0xFF" # 100%
- register "hwm_fan2_seg2_speed" = "0xD9" # 85%
- register "hwm_fan2_seg3_speed" = "0xB2" # 70%
- register "hwm_fan2_seg4_speed" = "0x99" # 60%
- register "hwm_fan2_seg5_speed" = "0x80" # 50%
- register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor
- device pnp 4e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 4e.3 off end # Parallel Port
- device pnp 4e.4 on # Hardware Monitor
- io 0x60 = 0x295
- irq 0x70 = 0
- end
- device pnp 4e.5 off # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 4e.6 off end # GPIO
- device pnp 4e.7 on end # WDT
- device pnp 4e.a off end # PME
- device pnp 4e.10 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 4e.11 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 4e.12 off # COM3
- io 0x60 = 0x3e8
- irq 0x70 = 4
- end
- device pnp 4e.13 off # COM4
- io 0x60 = 0x2e8
- irq 0x70 = 3
- end
- device pnp 4e.14 off # COM5
- end
- device pnp 4e.15 off # COM6
- end
- end # f81866d
- end #LPC
- device pci 14.7 on end # SD
- end #chip southbridge/amd/pi/hudson
-
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 18.5 on end
-
- end #domain
-end #northbridge/amd/pi/00730F01/root_complex
diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl
deleted file mode 100644
index 5567cf3b34..0000000000
--- a/src/mainboard/bap/ode_e21XX/dsdt.asl
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- OEM_ID,
- ACPI_TABLE_CREATOR,
- 0x00010001 /* OEM Revision */
- )
-{ /* Start of ASL file */
- /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
-
- /* Globals for the platform */
- #include "acpi/mainboard.asl"
-
- /* Describe the USB Overcurrent pins */
- #include "acpi/usb_oc.asl"
-
- /* PCI IRQ mapping for the Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/pcie.asl>
-
- /* Describe the processor tree (\_SB) */
- #include <cpu/amd/pi/00730F01/acpi/cpu.asl>
-
- /* Contains the supported sleep states for this chipset */
- #include <southbridge/amd/common/acpi/sleepstates.asl>
-
- /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
- #include "acpi/sleep.asl"
-
- /* System Bus */
- Scope(\_SB) { /* Start \_SB scope */
- /* global utility methods expected within the \_SB scope */
- #include <arch/x86/acpi/globutil.asl>
-
- /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
- #include "acpi/routing.asl"
-
- Device(PCI0) {
- /* Describe the AMD Northbridge */
- #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
-
- /* Describe the AMD Fusion Controller Hub Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/fch.asl>
- }
-
- /* Describe PCI INT[A-H] for the Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
- /* Add UART support for Windows */
- #include "acpi/superio.asl"
-
- } /* End \_SB scope */
-
- /* Describe SMBUS for the Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/smbus.asl>
-
- /* Define the General Purpose Events for the platform */
- #include "acpi/gpe.asl"
-
- /* Define the Thermal zones and methods for the platform */
- #include "acpi/thermal.asl"
-
- /* Define the System Indicators for the platform */
- #include "acpi/si.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/bap/ode_e21XX/irq_tables.c b/src/mainboard/bap/ode_e21XX/irq_tables.c
deleted file mode 100644
index ef31ff1e20..0000000000
--- a/src/mainboard/bap/ode_e21XX/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = 0;
- pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
-
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "%s done.\n", __func__);
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c
deleted file mode 100644
index ce4a63ccc3..0000000000
--- a/src/mainboard/bap/ode_e21XX/mainboard.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-
-/**********************************************
- * enable the dedicated function in mainboard.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c
deleted file mode 100644
index c5aeeb0b4e..0000000000
--- a/src/mainboard/bap/ode_e21XX/mptable.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/smp/mpspec.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-u8 picr_data[0x54] = {
- 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x03,0x04,0x05,0x07
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- u8 byte;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
deleted file mode 100644
index 6b116fd46f..0000000000
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <stdint.h>
-#include <amdblocks/acpimmio.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <superio/fintek/common/fintek.h>
-#include <superio/fintek/f81866d/f81866d.h>
-
-#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
-
-static void romstage_main_template(void)
-{
- u32 val;
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- pm_io_write8(0xd2, 0);
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
- post_code(0x31);
- console_init();
- }
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
- /* After AMD_INIT_ENV -> move to ramstage ? */
- pm_io_write8(0xea, 1);
-}