from Mark Wilkinson, some fixes.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 28 insertions, 109 deletions

diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
index 30bd43b86c..ce6f762985 100644
--- a/src/mainboard/via/epia/Config.lb
+++ b/src/mainboard/via/epia/Config.lb
@@ -1,86 +1,3 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
-uses CONFIG_ROM_STREAM
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default HAVE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=5
-object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-
 ##
 ## Compute the location and size of where this firmware image
 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
@@ -155,20 +72,20 @@ end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
 
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
 ##
 if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/i386/reset16.inc 
-	ldscript /cpu/i386/reset16.lds 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
 else
-	mainboardinit cpu/i386/reset32.inc 
-	ldscript /cpu/i386/reset32.lds 
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
 ### Should this be in the northbridge code?
@@ -210,10 +127,10 @@ mainboardinit ./auto.inc
 dir /pc80
 config chip.h
 
-northbridge via/vt8601 "vt8601"
+chip northbridge/via/vt8601
 #	pci 0:0.0
 #	pci 0:1.0
-	southbridge via/vt8231 "vt8231"
+	chip southbridge/via/vt8231
 #		pci 0:11.0
 #		pci 0:11.1
 #		pci 0:11.2
@@ -227,32 +144,38 @@ northbridge via/vt8601 "vt8601"
 		register "enable_com_ports" = "1"
 		register "enable_keyboard" = "0"
 		register "enable_nvram" = "1"
-                superio winbond/w83627hf link 1
-                        pnp 2e.0 on #  Floppy
+                chip superio/winbond/w83627hf
+                        device pnp 2e.0 on #  Floppy
                                  io 0x60 = 0x3f0
                                 irq 0x70 = 6
                                 drq 0x74 = 2
-                        pnp 2e.1 off #  Parallel Port
+			end
+                        device pnp 2e.1 off #  Parallel Port
                                  io 0x60 = 0x378
                                 irq 0x70 = 7
-                        pnp 2e.2 on #  Com1
+			end
+                        device pnp 2e.2 on #  Com1
                                  io 0x60 = 0x3f8
                                 irq 0x70 = 4
-                        pnp 2e.3 off #  Com2
+			end
+                        device pnp 2e.3 off #  Com2
                                 io 0x60 = 0x2f8
                                 irq 0x70 = 3
-                        pnp 2e.5 on #  Keyboard
+			end
+                        device pnp 2e.5 on #  Keyboard
                                  io 0x60 = 0x60
                                  io 0x62 = 0x64
                                irq 0x70 = 1
 				irq 0x72 = 12
-                        pnp 2e.6 off #  CIR
-                        pnp 2e.7 off #  GAME_MIDI_GIPO1
-                        pnp 2e.8 off #  GPIO2
-                        pnp 2e.9 off #  GPIO3
-                        pnp 2e.a off #  ACPI
-                        pnp 2e.b on  #  HW Monitor
+			end
+                        device pnp 2e.6 off end #  CIR
+                        device pnp 2e.7 off end #  GAME_MIDI_GIPO1
+                        device pnp 2e.8 off end #  GPIO2
+                        device pnp 2e.9 off end #  GPIO3
+                        device pnp 2e.a off end #  ACPI
+                        device pnp 2e.b on  #  HW Monitor
  				 io 0x60 = 0x290
+			end
 			register "com1" = "{1}"
 		#	register "com1" = "{1, 0, 0x3f8, 4}"
 		#	register "lpt" = "{1}"
@@ -260,10 +183,6 @@ northbridge via/vt8601 "vt8601"
 	end
 end
 
-cpu p6 "cpu0"
-	
-end
-
 ##
 ## Include the old serial code for those few places that still need it.
 ##