src/cpu: Remove unnecessary whitespace before "\n"

Change-Id: Iebdcc659bf2a3e738702c85ee86dbb71b504721a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16279
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

7 files changed, 8 insertions, 8 deletions

diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index b4f1ad32a9..7956523b78 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -122,7 +122,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk(BIOS_INFO, "if the IOAPIC device doesn't support 256 APIC id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for IOAPIC\n");
+		printk(BIOS_INFO, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for IOAPIC\n");
 		enable_apic_ext_id(nodes);
 	}
 
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index 9485ff494f..2e6e153508 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -134,7 +134,7 @@ static void enable_fid_change(u8 fid)
 		dword |= (u32) fid & 0x1F;
 		dword |= 1 << 5;	// enable
 		pci_write_config32(dev, 0xd4, dword);
-		printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
+		printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x\n", i,
 		       dword);
 	}
 }
@@ -758,7 +758,7 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
          * PstatMaxVal is going to be 0 on cold reset anyway ?
 	 */
         if (!(pci_read_config32(dev, 0xdc) & (~PS_MAX_VAL_MASK))) {
-  	   printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n");
+  	   printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1\n");
 	};
 
 	msr.lo &= ~0xFE000000;	// clear nbvid
diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c
index 41e32ebde3..819a056d40 100644
--- a/src/cpu/amd/geode_gx2/cpubug.c
+++ b/src/cpu/amd/geode_gx2/cpubug.c
@@ -355,5 +355,5 @@ void cpubug(void)
 	bug784();
 	bug118253();
 	disablememoryreadorder();
-	printk(BIOS_DEBUG, "Done cpubug fixes \n");
+	printk(BIOS_DEBUG, "Done cpubug fixes\n");
 }
diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c
index cf8c2e26e5..7e7d81b19d 100644
--- a/src/cpu/amd/geode_lx/cpubug.c
+++ b/src/cpu/amd/geode_lx/cpubug.c
@@ -80,5 +80,5 @@ void cpubug(void)
 {
 	pcideadlock();
 	disablememoryreadorder();
-	printk(BIOS_DEBUG, "Done cpubug fixes \n");
+	printk(BIOS_DEBUG, "Done cpubug fixes\n");
 }
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index f45f34e452..ec5744bdce 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -110,7 +110,7 @@ u32 get_apicid_base(u32 ioapic_num)
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
+		printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
 		enable_apic_ext_id(sysconf.nodes);
 	}
 
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index b0681414a1..136636c41c 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -65,7 +65,7 @@ static inline u32 read_microcode_rev(void)
 		"movl $0x01, %%eax\n\t"
 		"cpuid\n\t"
 		"movl $0x08b, %%ecx\n\t"
-		"rdmsr \n\t"
+		"rdmsr\n\t"
 		: /* outputs */
 		"=a" (msr.lo), "=d" (msr.hi)
 		: /* inputs */
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
index e84ef28b19..ade1ec4967 100644
--- a/src/cpu/via/nano/nano_init.c
+++ b/src/cpu/via/nano/nano_init.c
@@ -145,7 +145,7 @@ static void nano_init(struct device *dev)
 	/* We didn't test this on the Nano 1000/2000 series, so warn the user */
 	if(c.x86_mask < MODEL_NANO_3000_B0) {
 		printk(BIOS_EMERG, "WARNING: This CPU has not been tested. "
-				   "Please report any issues encountered. \n");
+				   "Please report any issues encountered.\n");
 	}
 	switch (c.x86_mask) {
 	case MODEL_NANO: