diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-12-05 22:06:23 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-12-07 07:19:37 +0100 |
| commit | 891b6c4d199418a08ba88e42d6c8945ce05205f1 (patch) | |
| tree | 2ca7ea2f3bb9a1ff295aaa52041d20c05935a936 /src | |
| parent | 26267a7a41312c3160604766d17f361dc80c2a52 (diff) | |
| download | coreboot-891b6c4d199418a08ba88e42d6c8945ce05205f1.tar.xz | |
mainboard/google/reef: adjust chromeos.fmd regions
- Drastically reduced RW_MRC_CACHE size to hold one update. Now
that this area isn't changing after every S5 entry there's no
need make it so large.
- ELOG area reduced by 4KiB for subsequent area alignment. In practice
this doesn't matter because the elog library only uses 4KiB bytes.
16KiB->12KiB is a nop.
- Moved RW_NVRAM for subsequent alignment.
- Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries
and sized to 64KiB multiples. This ensures updates don't need a
read-modify-write that could force a system into recovery if
an inopportune power event occurred.
BUG=chrome-os-partner:60492
BRANCH=reef
Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17727
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/reef/chromeos.fmd | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index c7e51eedc1..3c289a1fd4 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -12,32 +12,32 @@ FLASH 16M { RO_UNUSED@0x1bc000 0x40000 } } - MISC_RW@0x400000 0x4a000 { - UNIFIED_MRC_CACHE@0x0 0x40000 { + MISC_RW@0x400000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x2f000 - RW_VAR_MRC_CACHE@0x3f000 0x1000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 } - RW_ELOG@0x40000 0x4000 - RW_SHARED@0x44000 0x4000 { + RW_ELOG@0x21000 0x3000 + RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD@0x48000 0x2000 + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 } - RW_SECTION_A@0x44a000 0x477800 { + RW_SECTION_A@0x430000 0x480000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4677c0 - RW_FWID_A@0x4777c0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x46ffc0 + RW_FWID_A@0x47ffc0 0x40 } - RW_SECTION_B@0x8c1800 0x477800 { + RW_SECTION_B@0x8b0000 0x480000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4677c0 - RW_FWID_B@0x4777c0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x46ffc0 + RW_FWID_B@0x47ffc0 0x40 } - RW_NVRAM@0xd39000 0x6000 - RW_LEGACY(CBFS)@0xd3f000 0x200000 - BIOS_UNUSABLE@0xf3f000 0x40000 + RW_LEGACY(CBFS)@0xd30000 0x200000 + BIOS_UNUSABLE@0xf30000 0x4f000 DEVICE_EXTENSION@0xf7f000 0x80000 # Currently, it is required that the BIOS region be a multiple of 8KiB. # This is required so that the recovery mechanism can find SIGN_CSE |