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authorLee Leahy <leroy.p.leahy@intel.com>2016-06-08 13:19:05 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-06-09 22:50:00 +0200
commit9048384defbe752e03c4e2b9cc995820c60d0cd2 (patch)
tree23a2be807adaf4a1781ee33ab6352708eb3b1d21 /src
parent6735871531301f56384376c54d88bbc75b660e74 (diff)
downloadcoreboot-9048384defbe752e03c4e2b9cc995820c60d0cd2.tar.xz
vendorcode/intel/fsp1_1/checklist: romstage - Add car_stage_entry
Add car_stage_entry as an optional routine in the checklist. TEST=Build and run on Galileo Gen2 Change-Id: I52f6aefc2566beac01373dbebf3a43d35032a0df Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15129 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat1
-rw-r--r--src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
index e6bef6cf26..267673aed6 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
@@ -1,6 +1,7 @@
arch_segment_loaded
backup_top_of_ram
boot_device_init
+car_stage_entry
cbfs_master_header_locator
cbmem_fail_resume
clear_recovery_mode_switch
diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
index 2634566528..70f204db04 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
+++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
@@ -1,6 +1,7 @@
arch_segment_loaded
backup_top_of_ram
boot_device_init
+car_stage_entry
cbmem_fail_resume
clear_recovery_mode_switch
cpu_smi_handler