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author | Gabe Black <gabeblack@chromium.com> | 2013-01-17 22:26:36 -0800 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-01-18 22:14:14 +0100 |
commit | 929f9f171944082240c04507b3f6ac1b0a2c6b1e (patch) | |
tree | 8c690d08c8b8d0a6f893aef31262a58ac1bf87e5 /src | |
parent | fba42a793a67d8910b4ab7fdfb386bcda9896d13 (diff) | |
download | coreboot-929f9f171944082240c04507b3f6ac1b0a2c6b1e.tar.xz |
armv7: add a wrapper for romstage's main() for ARM ISA
This adds a wrapper around main() in romstage which is compiled using
-marm. This assumes that the bootblock branches to romstage in ARM
mode.
The long-term idea is to enforce ABI compatibility when handing off to
the next stage by using shims which are which are compiled in a pre-
determiend manner and leave the main portions of each stage up to
whatever the compiler wants. So it will eventually look like this:
1. bootblock_main (ARM/Thumb)
2. bootblock_exit (ARM)
3. romstage_entry (ARM)
4. romstage_main (ARM/Thumb)
(credit to Gabe Black for writing the patch, I'm just uploading it)
Change-Id: I4fdb8d2c6c2c0a7178bcb9154c378ddce0567309
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/2175
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/armv7/Makefile.inc | 15 | ||||
-rw-r--r-- | src/arch/armv7/romstage.ld | 1 | ||||
-rw-r--r-- | src/arch/armv7/romstage_main.c | 29 | ||||
-rw-r--r-- | src/mainboard/google/snow/romstage.c | 1 |
4 files changed, 42 insertions, 4 deletions
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index ecb5aee290..1d12eca3b7 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -265,21 +265,28 @@ endif ################################################################################ # Build the romstage +romstage_main_c = $(src)/arch/armv7/romstage_main.c +romstage_main_o = $(obj)/arch/armv7/romstage_main.o + +$(romstage_main_o): $(romstage_main_c) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -c -o $@ $< -marm + # FIXME(dhendrix): added debug printfs -$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld +$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(romstage_main_o) $(objgenerated)/romstage_null.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_null.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--start-group $(romstage-objs) $(romstage_main_o) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_xip.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) $(romstage_main_o) -T $(objgenerated)/romstage_xip.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--start-group $(romstage-objs) $(romstage_main_o) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index d40d2ef44a..faf7d6d38a 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -44,6 +44,7 @@ SECTIONS .romtext . : { _rom = .; _start = .; + *(.text.entry.armv7); *(.text.startup); *(.text); } diff --git a/src/arch/armv7/romstage_main.c b/src/arch/armv7/romstage_main.c new file mode 100644 index 0000000000..0b463b8f1f --- /dev/null +++ b/src/arch/armv7/romstage_main.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void main(void); + +/* romstage_main is simply a stub to invoke main(), to handle ARM mode switching + * (ARM/Thumb) properly. */ + +void romstage_main(void) __attribute__((section(".text.entry.armv7"))); +void romstage_main(void) +{ + main(); +} diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 9092b7cd86..e2af2c0c4e 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -26,6 +26,7 @@ static void mmu_setup(void) dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); } +void main(void); void main(void) { mmu_setup(); |