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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-07 15:17:48 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-12 16:01:05 +0000
commit93e08c75d3549570cdbf5777e4fafbf4719ad747 (patch)
treed42ac9ddb8d4083623eec3bc17fd15c8dfa23a78 /src
parent7f40bd667c6f02ef61f0f7dbf9eddab91db0ad28 (diff)
downloadcoreboot-93e08c75d3549570cdbf5777e4fafbf4719ad747.tar.xz
asus/p3b-f,intel/i440bx: Move enable/disable_spd() call
Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asus/p3b-f/romstage.c6
-rw-r--r--src/northbridge/intel/i440bx/raminit.c8
-rw-r--r--src/northbridge/intel/i440bx/raminit.h3
3 files changed, 13 insertions, 4 deletions
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index e9630bfdb0..8e254baa93 100644
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -49,7 +49,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
* 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28
* control which SMBus/I2C offsets can be accessed.
*/
-static void enable_spd(void)
+void enable_spd(void)
{
outb(0x6f, PM_IO_BASE + 0x37);
}
@@ -58,7 +58,7 @@ static void enable_spd(void)
* Disable SPD access after RAM init to allow access to SMBus/I2C offsets
* 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
*/
-static void disable_spd(void)
+void disable_spd(void)
{
outb(0x67, PM_IO_BASE + 0x37);
}
@@ -71,10 +71,8 @@ void mainboard_romstage_entry(void)
enable_smbus();
enable_pm();
- enable_spd();
sdram_initialize();
- disable_spd();
cbmem_initialize_empty();
}
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 0f9f2f652a..28b22ec675 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -1035,10 +1035,18 @@ void sdram_enable(void)
DUMPNORTH();
}
+/* Implemented under mainboard. */
+void __weak enable_spd(void) { }
+void __weak disable_spd(void) { }
+
void sdram_initialize(void)
{
+ enable_spd();
+
dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
+
+ disable_spd();
}
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index 448f8d69be..23299d1dd6 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -20,6 +20,9 @@
/* The 440BX supports up to four (single- or double-sided) DIMMs. */
#define DIMM_SOCKETS 4
+void enable_spd(void);
+void disable_spd(void);
+
/* Function prototypes. */
int spd_read_byte(unsigned int device, unsigned int address);
void sdram_set_registers(void);