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authorArthur Heymans <arthur@aheymans.xyz>2020-05-29 16:09:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-06-03 12:23:43 +0000
commit954a4a4d168caf264e6275deff5523d2863bdb19 (patch)
treebf226c2350c2ab3fda85c76fb4fb818bb600be41 /src
parentefbf638b9a500b1d31130299a1cce3a5b4d9e398 (diff)
downloadcoreboot-954a4a4d168caf264e6275deff5523d2863bdb19.tar.xz
mb/gigabyte/ga-g41m-es2l: Remove MEI PCI devices from devicetree
These devices never show on the PCI domain. Change-Id: I2d4d99c1e96c15dacb950aeb85b3e9a5d127c791 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
index 2b23ca1006..6328bc64a4 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -21,8 +21,6 @@ chip northbridge/intel/x4x # Northbridge
device pci 2.1 on # Integrated graphics controller 2
subsystemid 0x1458 0xd001
end
- device pci 3.0 off end # ME
- device pci 3.1 off end # ME
chip southbridge/intel/i82801gx # Southbridge
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"