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authorAngel Pons <th3fanbus@gmail.com>2020-10-26 00:17:52 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-13 13:17:31 +0000
commita0426267e330c60aa74528a06a0e130efe2ad32f (patch)
tree0758cce1d8739e398a41e351c89b1f31db26e73f /src
parenta472e33634b7c9709fccb3c60d1d21b2c75e1347 (diff)
downloadcoreboot-a0426267e330c60aa74528a06a0e130efe2ad32f.tar.xz
broadwell: Flatten `acpi_init_gnvs` function
Instead of relying on mainboards to call it, do like Lynx Point. Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46793 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/auron/acpi_tables.c2
-rw-r--r--src/mainboard/google/jecht/acpi_tables.c2
-rw-r--r--src/mainboard/intel/wtm2/acpi_tables.c2
-rw-r--r--src/mainboard/purism/librem_bdw/acpi_tables.c1
-rw-r--r--src/soc/intel/broadwell/acpi.c25
-rw-r--r--src/soc/intel/broadwell/pch/lpc.c25
6 files changed, 25 insertions, 32 deletions
diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c
index 970ec9d5cf..5284cef29f 100644
--- a/src/mainboard/google/auron/acpi_tables.c
+++ b/src/mainboard/google/auron/acpi_tables.c
@@ -8,8 +8,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs)
{
- acpi_init_gnvs(gnvs);
-
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c
index 580c0b6532..1197c0ca1c 100644
--- a/src/mainboard/google/jecht/acpi_tables.c
+++ b/src/mainboard/google/jecht/acpi_tables.c
@@ -9,8 +9,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs)
{
- acpi_init_gnvs(gnvs);
-
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c
index 53c8926fb6..21a94bca8d 100644
--- a/src/mainboard/intel/wtm2/acpi_tables.c
+++ b/src/mainboard/intel/wtm2/acpi_tables.c
@@ -9,8 +9,6 @@
void acpi_create_gnvs(struct global_nvs *gnvs)
{
- acpi_init_gnvs(gnvs);
-
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c
index df3d15e965..e127a56a26 100644
--- a/src/mainboard/purism/librem_bdw/acpi_tables.c
+++ b/src/mainboard/purism/librem_bdw/acpi_tables.c
@@ -7,5 +7,4 @@
void acpi_create_gnvs(struct global_nvs *gnvs)
{
- acpi_init_gnvs(gnvs);
}
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 3d5e74ae5c..7366642c62 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -148,31 +148,6 @@ static int get_cores_per_package(void)
return cores;
}
-void acpi_init_gnvs(struct global_nvs *gnvs)
-{
- /* Set unknown wake source */
- gnvs->pm1i = -1;
-
- /* CPU core count */
- gnvs->pcnt = dev_count_cpu();
-
-#if CONFIG(CONSOLE_CBMEM)
- /* Update the mem console pointer. */
- gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
-#endif
-
- if (CONFIG(CHROMEOS)) {
- /* Initialize Verified Boot data */
- chromeos_init_chromeos_acpi(&(gnvs->chromeos));
- if (CONFIG(EC_GOOGLE_CHROMEEC)) {
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
- } else {
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
- }
- }
-}
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 2111913a0e..73b83e4e09 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -13,6 +13,8 @@
#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
+#include <ec/google/chromeec/ec.h>
+#include <vendorcode/google/chromeos/gnvs.h>
#include <string.h>
#include <soc/gpio.h>
#include <soc/iobp.h>
@@ -621,6 +623,29 @@ static void southcluster_inject_dsdt(const struct device *device)
if (gnvs) {
acpi_create_gnvs(gnvs);
+
+ /* Set unknown wake source */
+ gnvs->pm1i = -1;
+
+ /* CPU core count */
+ gnvs->pcnt = dev_count_cpu();
+
+#if CONFIG(CONSOLE_CBMEM)
+ /* Update the mem console pointer. */
+ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
+#endif
+
+ if (CONFIG(CHROMEOS)) {
+ /* Initialize Verified Boot data */
+ chromeos_init_chromeos_acpi(&(gnvs->chromeos));
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+ gnvs->chromeos.vbt2 = google_ec_running_ro() ?
+ ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+ } else {
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+ }
+ }
+
/* And tell SMI about it */
apm_control(APM_CNT_GNVS_UPDATE);