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| author | Peter Lemenkov <lemenkov@gmail.com> | 2019-11-27 15:15:27 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-06 15:21:47 +0000 |
| commit | a0c97590b910da51dcd95547f720e9d3b964f140 (patch) | |
| tree | 7d9e57e666861ffc7134bd204b18d0b5a6ab5f32 /src | |
| parent | 2ee6fbf0d7593f0c78677c9c2bb307e47cea6c23 (diff) | |
| download | coreboot-a0c97590b910da51dcd95547f720e9d3b964f140.tar.xz | |
mb/lenovo/w520/devicetree: Use subsystemid inheritance
Change-Id: If7816992e717b4da585b16e5bbe67610c9af867d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/lenovo/t520/variants/w520/devicetree.cb | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index 8716046410..8b2cbe78e4 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -37,9 +37,13 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "2048" device domain 0 on + subsystemid 0x17aa 0x21cf inherit + device pci 00.0 on end # host bridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on end # vga controller + device pci 02.0 on + subsystemid 0x17aa 0x21d1 + end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -73,7 +77,9 @@ chip northbridge/intel/sandybridge device pci 16.1 off end device pci 16.2 off end device pci 16.3 off end - device pci 19.0 on end # Intel Gigabit Ethernet + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21ce + end device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 @@ -87,10 +93,10 @@ chip northbridge/intel/sandybridge device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end |