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| author | Paul Fagerburg <pfagerburg@chromium.org> | 2019-04-26 15:12:21 -0600 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-04-29 03:47:48 +0000 |
| commit | a1b187ab29f16532de413e2d315728cd01d9afca (patch) | |
| tree | a1be2eca3eb102cd8cf96f144047b54062ca6acd /src | |
| parent | d3d41b348d2af281c08529e7ba7832dca44d4ca9 (diff) | |
| download | coreboot-a1b187ab29f16532de413e2d315728cd01d9afca.tar.xz | |
mb/google/hatch/variants/baseboard: remove unused dqs_map
The dqs_map array is used only for LPDDR3 and LPDDR4. It is not used for
DDR4, and so it can be removed from the baseboard memory initialization
code.
BRANCH=none
BUG=b:129706819
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.
Change-Id: I07fac3097d68f37b4630d3f0010f987da2f03bd7
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32484
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/memory.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index b6a66150fa..580bdc9ab3 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -20,16 +20,6 @@ #include <string.h> static const struct cnl_mb_cfg baseboard_memcfg = { - /* - * The dqs_map arrays map the ddr4 pins to the SoC pins - * for both channels. - * - * the index = pin number on ddr4 part - * the value = pin number on SoC - */ - .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - /* Baseboard uses 121, 81 and 100 rcomp resistors */ .rcomp_resistor = { 121, 81, 100 }, |