vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197

Update FSP headers for Tiger Lake platform generated based FSP
version 3197 to include below additional UPD:

FSP-M:
SkipCpuReplacementCheck
PCH HSIO Tuning UPDs

FSP-S:
PcieRpHotPlug
TccActivationOffset
TccOffsetClamp
TccOffsetLock
TccOffsetTimeWindowForRatl
USB3 HSIO Tuning UPDs

BUG=none
BRANCH=none
TEST=build and boot volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ib40d226dd2ecc4fb34965e1f2c416c53edef01d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42243
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 260 insertions, 42 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
index a709858eb4..ade6b03b3b 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
@@ -676,7 +676,161 @@ typedef struct {
 
 /** Offset 0x0368 - Reserved
 **/
-  UINT8                      Reserved24[522];
+  UINT8                      Reserved24[87];
+
+/** Offset 0x03BF - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen1DownscaleAmpEnable[24];
+
+/** Offset 0x03D7 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+  PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchPcieHsioTxGen1DownscaleAmp[24];
+
+/** Offset 0x03EF - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen2DownscaleAmpEnable[24];
+
+/** Offset 0x0407 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+  PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchPcieHsioTxGen2DownscaleAmp[24];
+
+/** Offset 0x041F - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen3DownscaleAmpEnable[24];
+
+/** Offset 0x0437 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+  PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchPcieHsioTxGen3DownscaleAmp[24];
+
+/** Offset 0x044F - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen1DeEmphEnable[24];
+
+/** Offset 0x0467 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+  PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchPcieHsioTxGen1DeEmph[24];
+
+/** Offset 0x047F - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph3p5Enable[24];
+
+/** Offset 0x0497 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+  PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph3p5[24];
+
+/** Offset 0x04AF - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph6p0Enable[24];
+
+/** Offset 0x04C7 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+  PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchPcieHsioTxGen2DeEmph6p0[24];
+
+/** Offset 0x04DF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioRxGen1EqBoostMagEnable[8];
+
+/** Offset 0x04E7 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+  PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+  UINT8                       PchSataHsioRxGen1EqBoostMag[8];
+
+/** Offset 0x04EF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioRxGen2EqBoostMagEnable[8];
+
+/** Offset 0x04F7 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+  PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+  UINT8                       PchSataHsioRxGen2EqBoostMag[8];
+
+/** Offset 0x04FF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioRxGen3EqBoostMagEnable[8];
+
+/** Offset 0x0507 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+  PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+  UINT8                       PchSataHsioRxGen3EqBoostMag[8];
+
+/** Offset 0x050F - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen1DownscaleAmpEnable[8];
+
+/** Offset 0x0517 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+  PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchSataHsioTxGen1DownscaleAmp[8];
+
+/** Offset 0x051F - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen2DownscaleAmpEnable[8];
+
+/** Offset 0x0527 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
+  PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchSataHsioTxGen2DownscaleAmp[8];
+
+/** Offset 0x052F - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen3DownscaleAmpEnable[8];
+
+/** Offset 0x0537 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
+  PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+  UINT8                       PchSataHsioTxGen3DownscaleAmp[8];
+
+/** Offset 0x053F - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen1DeEmphEnable[8];
+
+/** Offset 0x0547 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+  PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchSataHsioTxGen1DeEmph[8];
+
+/** Offset 0x054F - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen2DeEmphEnable[8];
+
+/** Offset 0x0557 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+  PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchSataHsioTxGen2DeEmph[8];
+
+/** Offset 0x055F - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+  0: Disable; 1: Enable.
+**/
+  UINT8                       PchSataHsioTxGen3DeEmphEnable[8];
+
+/** Offset 0x0567 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
+  PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+  UINT8                       PchSataHsioTxGen3DeEmph[8];
+
+/** Offset 0x056F - Reserved
+**/
+  UINT8                       Reserved25[3];
 
 /** Offset 0x0572 - Number of RsvdSmbusAddressTable.
   The number of elements in the RsvdSmbusAddressTable.
@@ -685,7 +839,7 @@ typedef struct {
 
 /** Offset 0x0573 - Reserved
 **/
-  UINT8                       Reserved25[4];
+  UINT8                       Reserved26[4];
 
 /** Offset 0x0577 - Usage type for ClkSrc
   0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
@@ -700,7 +854,7 @@ typedef struct {
 
 /** Offset 0x0597 - Reserved
 **/
-  UINT8                       Reserved26[5];
+  UINT8                       Reserved27[5];
 
 /** Offset 0x059C - Enable PCIE RP Mask
   Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -723,7 +877,7 @@ typedef struct {
 
 /** Offset 0x05A2 - Reserved
 **/
-  UINT8                       Reserved27[14];
+  UINT8                       Reserved28[14];
 
 /** Offset 0x05B0 - ISA Serial Base selection
   Select ISA Serial Base address. Default is 0x3F8.
@@ -733,7 +887,7 @@ typedef struct {
 
 /** Offset 0x05B1 - Reserved
 **/
-  UINT8                       Reserved28[4];
+  UINT8                       Reserved29[4];
 
 /** Offset 0x05B5 - MRC Safe Config
   Enables/Disable MRC Safe Config
@@ -791,7 +945,7 @@ typedef struct {
 
 /** Offset 0x05BE - Reserved
 **/
-  UINT8                       Reserved29[2];
+  UINT8                       Reserved30[2];
 
 /** Offset 0x05C0 - Early Command Training
   Enables/Disable Early Command Training
@@ -801,7 +955,7 @@ typedef struct {
 
 /** Offset 0x05C1 - Reserved
 **/
-  UINT8                       Reserved30[102];
+  UINT8                       Reserved31[102];
 
 /** Offset 0x0627 - Rank Margin Tool Per Bit
   Enable/Disable Rank Margin Tool Per Bit
@@ -811,7 +965,7 @@ typedef struct {
 
 /** Offset 0x0628 - Reserved
 **/
-  UINT8                       Reserved31[6];
+  UINT8                       Reserved32[6];
 
 /** Offset 0x062E - Ch Hash Mask
   Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
@@ -821,7 +975,7 @@ typedef struct {
 
 /** Offset 0x0630 - Reserved
 **/
-  UINT8                      Reserved32[62];
+  UINT8                      Reserved33[62];
 
 /** Offset 0x066E - PcdSerialDebugLevel
   Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
@@ -834,7 +988,7 @@ typedef struct {
 
 /** Offset 0x066F - Reserved
 **/
-  UINT8                       Reserved33[2];
+  UINT8                       Reserved34[2];
 
 /** Offset 0x0671 - Safe Mode Support
   This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
@@ -844,7 +998,7 @@ typedef struct {
 
 /** Offset 0x0672 - Reserved
 **/
-  UINT8                       Reserved34[2];
+  UINT8                       Reserved35[2];
 
 /** Offset 0x0674 - TCSS USB Port Enable
   Bitmap for per port enabling
@@ -853,7 +1007,7 @@ typedef struct {
 
 /** Offset 0x0675 - Reserved
 **/
-  UINT8                       Reserved35[71];
+  UINT8                       Reserved36[71];
 
 /** Offset 0x06BC - Command Pins Mirrored
   BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -863,7 +1017,7 @@ typedef struct {
 
 /** Offset 0x06C0 - Reserved
 **/
-  UINT8                       Reserved36[5];
+  UINT8                       Reserved37[5];
 
 /** Offset 0x06C5 - Skip external display device scanning
   Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -874,7 +1028,7 @@ typedef struct {
 
 /** Offset 0x06C6 - Reserved
 **/
-  UINT8                       Reserved37[2];
+  UINT8                       Reserved38[2];
 
 /** Offset 0x06C8 - Lock PCU Thermal Management registers
   Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
@@ -884,7 +1038,7 @@ typedef struct {
 
 /** Offset 0x06C9 - Reserved
 **/
-  UINT8                       Reserved38[122];
+  UINT8                       Reserved39[122];
 
 /** Offset 0x0743 - Enable HD Audio Link
   Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
@@ -894,7 +1048,7 @@ typedef struct {
 
 /** Offset 0x0744 - Reserved
 **/
-  UINT8                       Reserved39[3];
+  UINT8                       Reserved40[3];
 
 /** Offset 0x0747 - Enable HD Audio DMIC_N Link
   Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
@@ -903,7 +1057,7 @@ typedef struct {
 
 /** Offset 0x0749 - Reserved
 **/
-  UINT8                       Reserved40[3];
+  UINT8                       Reserved41[3];
 
 /** Offset 0x074C - DMIC<N> ClkA Pin Muxing (N - DMIC number)
   Determines DMIC<N> ClkA Pin muxing. See  GPIO_*_MUXING_DMIC<N>_CLKA_*
@@ -923,7 +1077,7 @@ typedef struct {
 
 /** Offset 0x075D - Reserved
 **/
-  UINT8                       Reserved41[3];
+  UINT8                       Reserved42[3];
 
 /** Offset 0x0760 - DMIC<N> Data Pin Muxing
   Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -960,7 +1114,17 @@ typedef struct {
 
 /** Offset 0x0775 - Reserved
 **/
-  UINT8                       Reserved42[297];
+  UINT8                       Reserved43[295];
+
+/** Offset 0x089C - Skip CPU replacement check
+  Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
+  $EN_DIS
+**/
+  UINT8                       SkipCpuReplacementCheck;
+
+/** Offset 0x089D - Reserved
+**/
+  UINT8                       Reserved44;
 
 /** Offset 0x089E - Serial Io Uart Debug Mode
   Select SerialIo Uart Controller mode
@@ -971,7 +1135,7 @@ typedef struct {
 
 /** Offset 0x089F - Reserved
 **/
-  UINT8                       Reserved43[121];
+  UINT8                       Reserved45[121];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
index 8f5e6d046b..46492de52c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
@@ -633,9 +633,10 @@ typedef struct {
 **/
   UINT8                       RtcMemoryLock;
 
-/** Offset 0x0622 - Reserved
+/** Offset 0x0622 - Enable PCIE RP HotPlug
+  Indicate whether the root port is hot plug available.
 **/
-  UINT8                       Reserved34[24];
+  UINT8                       PcieRpHotPlug[24];
 
 /** Offset 0x063A - Enable PCIE RP Pm Sci
   Indicate whether the root port power manager SCI is enabled.
@@ -644,7 +645,7 @@ typedef struct {
 
 /** Offset 0x0652 - Reserved
 **/
-  UINT8                       Reserved35[24];
+  UINT8                       Reserved34[24];
 
 /** Offset 0x066A - Enable PCIE RP Clk Req Detect
   Probe CLKREQ# signal before enabling CLKREQ# based power management.
@@ -658,7 +659,7 @@ typedef struct {
 
 /** Offset 0x069A - Reserved
 **/
-  UINT8                       Reserved36[168];
+  UINT8                       Reserved35[168];
 
 /** Offset 0x0742 - PCIE RP Max Payload
   Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
@@ -673,7 +674,7 @@ typedef struct {
 
 /** Offset 0x075B - Reserved
 **/
-  UINT8                       Reserved37[5];
+  UINT8                       Reserved36[5];
 
 /** Offset 0x0760 - Touch Host Controller Port 1 Assignment
   Assign THC Port 1
@@ -683,7 +684,7 @@ typedef struct {
 
 /** Offset 0x0761 - Reserved
 **/
-  UINT8                       Reserved38[79];
+  UINT8                       Reserved37[79];
 
 /** Offset 0x07B0 - PCIE RP Aspm
   The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
@@ -704,7 +705,7 @@ typedef struct {
 
 /** Offset 0x07F8 - Reserved
 **/
-  UINT8                       Reserved39[79];
+  UINT8                       Reserved38[79];
 
 /** Offset 0x0847 - PCH Pm WoW lan Enable
   Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
@@ -727,7 +728,7 @@ typedef struct {
 
 /** Offset 0x084A - Reserved
 **/
-  UINT8                       Reserved40[16];
+  UINT8                       Reserved39[16];
 
 /** Offset 0x085A - PCH Sata Pwr Opt Enable
   SATA Power Optimizer on PCH side.
@@ -737,7 +738,7 @@ typedef struct {
 
 /** Offset 0x085B - Reserved
 **/
-  UINT8                       Reserved41[42];
+  UINT8                       Reserved40[42];
 
 /** Offset 0x0885 - Enable SATA Port Enable Dito Config
   Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
@@ -751,7 +752,7 @@ typedef struct {
 
 /** Offset 0x0895 - Reserved
 **/
-  UINT8                       Reserved42;
+  UINT8                       Reserved41;
 
 /** Offset 0x0896 - Enable SATA Port DmVal
   DEVSLP Idle Timeout (DITO), Default is 625.
@@ -760,7 +761,7 @@ typedef struct {
 
 /** Offset 0x08A6 - Reserved
 **/
-  UINT8                       Reserved43[72];
+  UINT8                       Reserved42[72];
 
 /** Offset 0x08EE - USB2 Port Over Current Pin
   Describe the specific over current pin number of USB 2.0 Port N.
@@ -774,7 +775,7 @@ typedef struct {
 
 /** Offset 0x0908 - Reserved
 **/
-  UINT8                       Reserved44[16];
+  UINT8                       Reserved43[16];
 
 /** Offset 0x0918 - Enable 8254 Static Clock Gating
   Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
@@ -794,7 +795,7 @@ typedef struct {
 
 /** Offset 0x091A - Reserved
 **/
-  UINT8                       Reserved45[3];
+  UINT8                       Reserved44[3];
 
 /** Offset 0x091D - Hybrid Storage Detection and Configuration Mode
   Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
@@ -805,7 +806,7 @@ typedef struct {
 
 /** Offset 0x091E - Reserved
 **/
-  UINT8                       Reserved46[96];
+  UINT8                       Reserved45[96];
 
 /** Offset 0x097E - USB2 Port Reset Message Enable
   0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
@@ -814,7 +815,7 @@ typedef struct {
 
 /** Offset 0x098E - Reserved
 **/
-  UINT8                       Reserved47[322];
+  UINT8                       Reserved46[322];
 
 /** Offset 0x0AD0 - RpPtmBytes
 **/
@@ -822,7 +823,23 @@ typedef struct {
 
 /** Offset 0x0AD4 - Reserved
 **/
-  UINT8                      Reserved48[101];
+  UINT8                      Reserved47[36];
+
+/** Offset 0x0AF8 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
+  value in array can be between 0-1. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate2UniqTranEnable[10];
+
+/** Offset 0x0B02 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+  USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
+  <b>Default = 4Ch</b>. One byte for each port.
+**/
+  UINT8                       Usb3HsioTxRate2UniqTran[10];
+
+/** Offset 0x0B0C - Reserved
+**/
+  UINT8                       Reserved48[45];
 
 /** Offset 0x0B39 - GT Frequency Limit
   0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
@@ -840,7 +857,34 @@ typedef struct {
 
 /** Offset 0x0B3A - Reserved
 **/
-  UINT8                       Reserved49[80];
+  UINT8                       Reserved49[31];
+
+/** Offset 0x0B59 - TCC Activation Offset
+  TCC Activation Offset. Offset from factory set TCC activation temperature at which
+  the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
+  Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
+  <b>10</b>, For all other SKUs the recommended default are <b>0</b>
+**/
+  UINT8                       TccActivationOffset;
+
+/** Offset 0x0B5A - Tcc Offset Clamp Enable/Disable
+  Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
+  below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
+  For all other SKUs the recommended default are  <b>0: Disabled</b>.
+  $EN_DIS
+**/
+  UINT8                       TccOffsetClamp;
+
+/** Offset 0x0B5B - Tcc Offset Lock
+  Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
+  target; <b>0: Disabled</b>; 1: Enabled.
+  $EN_DIS
+**/
+  UINT8                       TccOffsetLock;
+
+/** Offset 0x0B5C - Reserved
+**/
+  UINT8                       Reserved50[46];
 
 /** Offset 0x0B8A - TimeUnit for C-State Latency Control5
   TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
@@ -850,7 +894,17 @@ typedef struct {
 
 /** Offset 0x0B8B - Reserved
 **/
-  UINT8                       Reserved50[179];
+  UINT8                       Reserved51[89];
+
+/** Offset 0x0BE4 - Tcc Offset Time Window for RATL
+  Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+  Range 0 to 4095875 in Step size of 125
+**/
+  UINT32                      TccOffsetTimeWindowForRatl;
+
+/** Offset 0x0BE8 - Reserved
+**/
+  UINT8                      Reserved52[86];
 
 /** Offset 0x0C3E - Enable LOCKDOWN SMI
   Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
@@ -872,7 +926,7 @@ typedef struct {
 
 /** Offset 0x0C41 - Reserved
 **/
-  UINT8                       Reserved51;
+  UINT8                       Reserved53;
 
 /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency
   Latency Tolerance Reporting, Max Snoop Latency.
@@ -886,7 +940,7 @@ typedef struct {
 
 /** Offset 0x0CA2 - Reserved
 **/
-  UINT8                       Reserved52[269];
+  UINT8                       Reserved54[269];
 
 /** Offset 0x0DAF - LpmStateEnableMask
 **/
@@ -894,7 +948,7 @@ typedef struct {
 
 /** Offset 0x0DB0 - Reserved
 **/
-  UINT8                       Reserved53[232];
+  UINT8                       Reserved55[232];
 } FSP_S_CONFIG;
 
 /** Fsp S UPD Configuration
@@ -911,7 +965,7 @@ typedef struct {
 
 /** Offset 0x0E98
 **/
-  UINT8                       UnusedUpdSpace35[6];
+  UINT8                       UnusedUpdSpace36[6];
 
 /** Offset 0x0E9E
 **/