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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-06-01 16:09:21 +1000
committerIdwer Vollering <vidwer@gmail.com>2014-06-01 13:34:47 +0200
commita34a1da44d9b16c0515325cecd5b23d15ab9c2cf (patch)
tree7762004c42a53b84a8a784c24480239a6d6b059c /src
parentee62164bb2052b065e72c5202c221b600401e0bc (diff)
downloadcoreboot-a34a1da44d9b16c0515325cecd5b23d15ab9c2cf.tar.xz
northbridge/intel/i945/i945.h: Trivial, fixup header guards
Change-Id: Iff15ab436e5b7b4e189c7341e7c508faaef07a3a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5896 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/i945/i945.h12
1 files changed, 7 insertions, 5 deletions
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index d4d35a2fa7..728fe0a8ff 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __NORTHBRIDGE_INTEL_I945_I945_H__
-#define __NORTHBRIDGE_INTEL_I945_I945_H__ 1
+#ifndef NORTHBRIDGE_INTEL_I945_H
+#define NORTHBRIDGE_INTEL_I945_H
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
@@ -58,9 +58,10 @@
#define DEVEN_D1F0 (1 << 1)
#define DEVEN_D2F0 (1 << 3)
#define DEVEN_D2F1 (1 << 4)
+
#ifndef BOARD_DEVEN
#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
-#endif
+#endif /* BOARD_DEVEN */
#define BSM 0x5c
@@ -360,5 +361,6 @@ void dump_pci_devices(void);
void dump_spd_registers(void);
void dump_mem(unsigned start, unsigned end);
-#endif
-#endif
+#endif /* __ACPI__ */
+
+#endif /* NORTHBRIDGE_INTEL_I945_H */