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authorRonald G. Minnich <rminnich@gmail.com>2006-03-14 20:01:51 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-03-14 20:01:51 +0000
commita41ff52ba9eceb0ef72eddc8f2c14be5751d85a3 (patch)
tree82823eb572ec1c2a2bae80db5451fa57ac9b6e37 /src
parentc994c973c654817f5e764615776b78b84cd21910 (diff)
downloadcoreboot-a41ff52ba9eceb0ef72eddc8f2c14be5751d85a3.tar.xz
Make the pll stuff parameterized.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/rumba/auto.c4
-rw-r--r--src/northbridge/amd/gx2/pll_reset.c8
2 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 19f7049c8e..6b2fd758c0 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -40,6 +40,10 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
#include "northbridge/amd/gx2/raminit.c"
#include "sdram/generic_sdram.c"
+#define PLLMSRhi 0x00001490
+#define PLLMSRlo 0x02000030
+#define PLLMSRhi2 ((0xde << 16) | (1 << 26) | (1 << 24))
+#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
#include "northbridge/amd/gx2/pll_reset.c"
static void msr_init(void)
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index 0e3a3caf95..248f422cc0 100644
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -133,15 +133,15 @@ static void pll_reset(void)
if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
print_debug("disable PLL bypass\n\r");
- msr.hi = 0x00001490;
- msr.lo = 0x02000030;
+ msr.hi = PLLMSRhi;
+ msr.lo = PLLMSRlo;
wrmsr(GLCP_SYS_RSTPLL, msr);
- msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
+ msr.lo |= PLLMSRhi2;
wrmsr(GLCP_SYS_RSTPLL, msr);
print_debug("Reset PLL\n\r");
- msr.lo |= ((1<<14) |(1<<13) | (1<<0));
+ msr.lo |= PLLMSRlo2;
wrmsr(GLCP_SYS_RSTPLL,msr);
print_debug("should not be here\n\r");
}