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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-28 17:45:13 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-30 11:42:07 +0000 |
| commit | a75ab2c46d2f7f14511cfa47a716eb394bdb5415 (patch) | |
| tree | 61f9bcddd3da55cf9e910b76eed9588c9bbf3652 /src | |
| parent | 05a7ffa25be465aea7a7aa22fdf443322abd95cf (diff) | |
| download | coreboot-a75ab2c46d2f7f14511cfa47a716eb394bdb5415.tar.xz | |
cpu/intel/car: Drop remains of setup_stack_and_mtrrs()
Platforms have moved to POSTCAR_STAGE=y.
Change-Id: I79c87e546805dbe0a4c28ed95f4d12666734eb79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/car/romstage.c | 3 | ||||
| -rw-r--r-- | src/include/cpu/intel/romstage.h | 17 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/romstage.h | 1 |
4 files changed, 0 insertions, 28 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 823853ce60..1109d80442 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -50,9 +50,6 @@ asmlinkage void *romstage_main(unsigned long bist) printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } - if (!IS_ENABLED(CONFIG_POSTCAR_STAGE)) - return setup_stack_and_mtrrs(); - platform_enter_postcar(); /* We do not return. */ diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h index 418d029642..726a184eb1 100644 --- a/src/include/cpu/intel/romstage.h +++ b/src/include/cpu/intel/romstage.h @@ -5,23 +5,6 @@ void mainboard_romstage_entry(unsigned long bist); -/* romstage_main is called from the cache-as-ram assembly file. The return - * value is the stack value to be used for romstage once cache-as-ram is - * torn down. The following values are pushed onto the stack to setup the - * MTRRs: - * +0: Number of MTRRs - * +4: MTRR base 0 31:0 - * +8: MTRR base 0 63:32 - * +12: MTRR mask 0 31:0 - * +16: MTRR mask 0 63:32 - * +20: MTRR base 1 31:0 - * +24: MTRR base 1 63:32 - * +28: MTRR mask 1 31:0 - * +32: MTRR mask 1 63:32 - * ... - */ -void *setup_stack_and_mtrrs(void); - void platform_enter_postcar(void); /* romstage_main is called from the cache-as-ram assembly file to prepare diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 011840461a..a52d3b1c2d 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -230,13 +230,6 @@ void romstage_common(struct romstage_params *params) romstage_handoff_init(prev_sleep_state == ACPI_S3); } -static inline uint32_t *stack_push(u32 *stack, u32 value) -{ - stack = &stack[-1]; - *stack = value; - return stack; -} - #define ROMSTAGE_RAM_STACK_SIZE 0x5000 /* setup_stack_and_mtrrs() determines the stack to use after diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index e2f99f252b..17d711fc25 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -32,7 +32,6 @@ void romstage_common(struct romstage_params *params); asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_lo, uint32_t tsc_high); void raminit(struct pei_data *pei_data); -void *setup_stack_and_mtrrs(void); struct chipset_power_state; struct chipset_power_state *fill_power_state(void); |