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| author | Zheng Bao <zheng.bao@amd.com> | 2009-06-03 03:15:05 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2009-06-03 03:15:05 +0000 |
| commit | a922b3195b77a3cc82bafad20dd3dfcfd2a61bc0 (patch) | |
| tree | fbe58f136039f1c35ab5fea76fcd7970b63a3a3e /src | |
| parent | f8318fe8f9af3d92eaf24aea3457a011e5fde134 (diff) | |
| download | coreboot-a922b3195b77a3cc82bafad20dd3dfcfd2a61bc0.tar.xz | |
Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/amd/rs690/rs690_pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c index 640fa75613..e0fc59d5cf 100644 --- a/src/southbridge/amd/rs690/rs690_pcie.c +++ b/src/southbridge/amd/rs690/rs690_pcie.c @@ -148,7 +148,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) /* waits until SB has trained to L0, poll for bit0-5 = 0x10 */ do { reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0); - reg &= 0x1f; /* remain LSB 5 bits */ + reg &= 0x3f; /* remain LSB [5:0] bits */ } while (LC_STATE_RECONFIG_GPPSB != reg); /* ensures that virtual channel negotiation is completed. poll for bit1 = 0 */ |