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| author | Tim Chen <tim-chen@quanta.corp-partner.google.com> | 2020-04-23 15:48:17 +0800 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-04-30 06:44:08 +0000 |
| commit | a932f6e507e1e77755c9670f0ee6aaf77ca5d83c (patch) | |
| tree | af7bc37974624847ded914c53a80e0a7d70244cb /src | |
| parent | 6c1a669b444fc7e6d7542ff910deca1a606d4c29 (diff) | |
| download | coreboot-a932f6e507e1e77755c9670f0ee6aaf77ca5d83c.tar.xz | |
mb/google/puff: update USB2 strength
Based on USB SI report to fine tune the strength for USB2 port0.
BRANCH=none
BUG=b:153590143
TEST=build and test USB2 port0 function works fine.
Change-Id: I070c9e1c8153a680fb8f827889738a764d7ea9f4
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src')
3 files changed, 24 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index ade12c5806..d7acbd71e7 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -21,7 +21,14 @@ chip soc/intel/cannonlake }" # USB configuration - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 register "usb2_ports[1]" = "{ .enable = 1, .ocpin = OC1, diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index e2380f4460..f5e85bde23 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -21,7 +21,14 @@ chip soc/intel/cannonlake }" # USB configuration - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 register "usb2_ports[1]" = "{ .enable = 1, .ocpin = OC1, diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d869b28a33..31efc4a1d9 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -24,7 +24,14 @@ chip soc/intel/cannonlake # NOTE: This only applies to Puff, # usb2_ports[1] and usb2_ports[3] were swapped on # reference schematics after Puff has been built. - register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2 + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[2]" = "{ .enable = 1, |